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@@ -224,14 +224,7 @@
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#define RESUME_TERMINATE (1 << 0)
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#define RESUME_TERMINATE (1 << 0)
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#define TTBCR2_SEP_SHIFT 15
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#define TTBCR2_SEP_SHIFT 15
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-#define TTBCR2_SEP_MASK 0x7
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-
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-#define TTBCR2_ADDR_32 0
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-#define TTBCR2_ADDR_36 1
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-#define TTBCR2_ADDR_40 2
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-#define TTBCR2_ADDR_42 3
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-#define TTBCR2_ADDR_44 4
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-#define TTBCR2_ADDR_48 5
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+#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
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#define TTBRn_HI_ASID_SHIFT 16
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#define TTBRn_HI_ASID_SHIFT 16
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@@ -793,26 +786,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
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if (smmu->version > ARM_SMMU_V1) {
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if (smmu->version > ARM_SMMU_V1) {
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reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
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reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
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- switch (smmu->va_size) {
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- case 32:
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- reg |= (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
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- break;
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- case 36:
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- reg |= (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
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- break;
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- case 40:
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- reg |= (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
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- break;
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- case 42:
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- reg |= (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
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- break;
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- case 44:
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- reg |= (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
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- break;
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- case 48:
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- reg |= (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
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- break;
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- }
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+ reg |= TTBCR2_SEP_UPSTREAM;
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
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}
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}
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} else {
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} else {
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