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@@ -114,8 +114,8 @@ static inline void neo_set_cts_flow_control(struct channel_t *ch)
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writeb(efr, &ch->ch_neo_uart->efr);
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/* Turn on table D, with 8 char hi/low watermarks */
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- writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY),
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- &ch->ch_neo_uart->fctr);
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+ writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
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+ &ch->ch_neo_uart->fctr);
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/* Feed the UART our trigger levels */
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writeb(8, &ch->ch_neo_uart->tfifo);
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@@ -149,8 +149,8 @@ static inline void neo_set_rts_flow_control(struct channel_t *ch)
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/* Turn on UART enhanced bits */
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writeb(efr, &ch->ch_neo_uart->efr);
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- writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY),
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- &ch->ch_neo_uart->fctr);
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+ writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
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+ &ch->ch_neo_uart->fctr);
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ch->ch_r_watermark = 4;
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writeb(32, &ch->ch_neo_uart->rfifo);
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@@ -187,7 +187,7 @@ static inline void neo_set_ixon_flow_control(struct channel_t *ch)
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/* Turn on UART enhanced bits */
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writeb(efr, &ch->ch_neo_uart->efr);
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- writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
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+ writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
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&ch->ch_neo_uart->fctr);
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ch->ch_r_watermark = 4;
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@@ -226,8 +226,8 @@ static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
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writeb(efr, &ch->ch_neo_uart->efr);
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/* Turn on table D, with 8 char hi/low watermarks */
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- writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
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- &ch->ch_neo_uart->fctr);
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+ writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
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+ &ch->ch_neo_uart->fctr);
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writeb(8, &ch->ch_neo_uart->tfifo);
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ch->ch_t_tlevel = 8;
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@@ -267,8 +267,8 @@ static inline void neo_set_no_input_flow_control(struct channel_t *ch)
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writeb(efr, &ch->ch_neo_uart->efr);
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/* Turn on table D, with 8 char hi/low watermarks */
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- writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
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- &ch->ch_neo_uart->fctr);
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+ writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
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+ &ch->ch_neo_uart->fctr);
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ch->ch_r_watermark = 0;
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@@ -305,8 +305,8 @@ static inline void neo_set_no_output_flow_control(struct channel_t *ch)
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writeb(efr, &ch->ch_neo_uart->efr);
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/* Turn on table D, with 8 char hi/low watermarks */
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- writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY),
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- &ch->ch_neo_uart->fctr);
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+ writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
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+ &ch->ch_neo_uart->fctr);
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ch->ch_r_watermark = 0;
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@@ -1353,7 +1353,7 @@ static void neo_flush_uart_read(struct channel_t *ch)
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if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
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return;
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- writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR),
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+ writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
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&ch->ch_neo_uart->isr_fcr);
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neo_pci_posting_flush(ch->ch_bd);
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@@ -1628,7 +1628,7 @@ static void neo_uart_init(struct channel_t *ch)
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/* Clear out UART and FIFO */
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readb(&ch->ch_neo_uart->txrx);
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- writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
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+ writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
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&ch->ch_neo_uart->isr_fcr);
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readb(&ch->ch_neo_uart->lsr);
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readb(&ch->ch_neo_uart->msr);
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