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@@ -458,6 +458,25 @@ static void sh_eth_chip_reset(struct net_device *ndev)
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mdelay(1);
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}
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+static void sh_eth_set_rate_gether(struct net_device *ndev)
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+{
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+ struct sh_eth_private *mdp = netdev_priv(ndev);
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+
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+ switch (mdp->speed) {
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+ case 10: /* 10BASE */
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+ sh_eth_write(ndev, GECMR_10, GECMR);
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+ break;
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+ case 100:/* 100BASE */
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+ sh_eth_write(ndev, GECMR_100, GECMR);
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+ break;
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+ case 1000: /* 1000BASE */
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+ sh_eth_write(ndev, GECMR_1000, GECMR);
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+ break;
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+ default:
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+ break;
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+ }
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+}
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+
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#ifdef CONFIG_OF
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/* R7S72100 */
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static struct sh_eth_cpu_data r7s72100_data = {
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@@ -489,6 +508,49 @@ static struct sh_eth_cpu_data r7s72100_data = {
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.tsu = 1,
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.shift_rd0 = 1,
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};
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+
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+static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
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+{
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+ struct sh_eth_private *mdp = netdev_priv(ndev);
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+
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+ /* reset device */
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+ sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
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+ mdelay(1);
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+
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+ sh_eth_select_mii(ndev);
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+}
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+
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+/* R8A7740 */
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+static struct sh_eth_cpu_data r8a7740_data = {
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+ .chip_reset = sh_eth_chip_reset_r8a7740,
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+ .set_duplex = sh_eth_set_duplex,
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+ .set_rate = sh_eth_set_rate_gether,
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+
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+ .register_type = SH_ETH_REG_GIGABIT,
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+
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+ .ecsr_value = ECSR_ICD | ECSR_MPD,
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+ .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
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+ .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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+
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+ .tx_check = EESR_TC1 | EESR_FTC,
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+ .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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+ EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
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+ EESR_TDE | EESR_ECI,
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+ .fdr_value = 0x0000070f,
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+
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+ .apr = 1,
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+ .mpr = 1,
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+ .tpauser = 1,
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+ .bculr = 1,
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+ .hw_swap = 1,
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+ .rpadir = 1,
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+ .rpadir_value = 2 << 16,
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+ .no_trimd = 1,
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+ .no_ade = 1,
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+ .tsu = 1,
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+ .select_mii = 1,
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+ .shift_rd0 = 1,
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+};
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#endif /* CONFIG_OF */
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/* There is CPU dependent code */
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@@ -715,25 +777,6 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
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.tsu = 1,
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};
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-static void sh_eth_set_rate_gether(struct net_device *ndev)
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-{
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- struct sh_eth_private *mdp = netdev_priv(ndev);
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-
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- switch (mdp->speed) {
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- case 10: /* 10BASE */
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- sh_eth_write(ndev, GECMR_10, GECMR);
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- break;
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- case 100:/* 100BASE */
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- sh_eth_write(ndev, GECMR_100, GECMR);
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- break;
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- case 1000: /* 1000BASE */
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- sh_eth_write(ndev, GECMR_1000, GECMR);
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- break;
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- default:
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- break;
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- }
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-}
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-
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/* SH7734 */
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static struct sh_eth_cpu_data sh7734_data = {
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.chip_reset = sh_eth_chip_reset,
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@@ -791,49 +834,6 @@ static struct sh_eth_cpu_data sh7763_data = {
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.irq_flags = IRQF_SHARED,
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};
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-static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
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-{
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- struct sh_eth_private *mdp = netdev_priv(ndev);
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-
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- /* reset device */
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- sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
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- mdelay(1);
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-
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- sh_eth_select_mii(ndev);
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-}
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-
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-/* R8A7740 */
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-static struct sh_eth_cpu_data r8a7740_data = {
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- .chip_reset = sh_eth_chip_reset_r8a7740,
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- .set_duplex = sh_eth_set_duplex,
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- .set_rate = sh_eth_set_rate_gether,
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-
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- .register_type = SH_ETH_REG_GIGABIT,
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-
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- .ecsr_value = ECSR_ICD | ECSR_MPD,
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- .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
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- .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
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-
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- .tx_check = EESR_TC1 | EESR_FTC,
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- .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
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- EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
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- EESR_TDE | EESR_ECI,
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- .fdr_value = 0x0000070f,
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-
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- .apr = 1,
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- .mpr = 1,
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- .tpauser = 1,
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- .bculr = 1,
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- .hw_swap = 1,
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- .rpadir = 1,
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- .rpadir_value = 2 << 16,
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- .no_trimd = 1,
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- .no_ade = 1,
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- .tsu = 1,
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- .select_mii = 1,
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- .shift_rd0 = 1,
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-};
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-
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static struct sh_eth_cpu_data sh7619_data = {
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.register_type = SH_ETH_REG_FAST_SH3_SH2,
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@@ -3281,7 +3281,6 @@ static struct platform_device_id sh_eth_id_table[] = {
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{ "sh7757-ether", (kernel_ulong_t)&sh7757_data },
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{ "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
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{ "sh7763-gether", (kernel_ulong_t)&sh7763_data },
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- { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
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{ "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
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{ }
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};
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