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@@ -462,32 +462,53 @@ static int lan78xx_read_raw_eeprom(struct lan78xx_net *dev, u32 offset,
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u32 length, u8 *data)
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{
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u32 val;
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+ u32 saved;
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int i, ret;
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+ int retval;
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- ret = lan78xx_eeprom_confirm_not_busy(dev);
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- if (ret)
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- return ret;
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+ /* depends on chip, some EEPROM pins are muxed with LED function.
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+ * disable & restore LED function to access EEPROM.
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+ */
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+ ret = lan78xx_read_reg(dev, HW_CFG, &val);
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+ saved = val;
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+ if ((dev->devid & ID_REV_CHIP_ID_MASK_) == 0x78000000) {
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+ val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
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+ ret = lan78xx_write_reg(dev, HW_CFG, val);
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+ }
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+
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+ retval = lan78xx_eeprom_confirm_not_busy(dev);
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+ if (retval)
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+ return retval;
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for (i = 0; i < length; i++) {
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val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_;
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val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
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ret = lan78xx_write_reg(dev, E2P_CMD, val);
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- if (unlikely(ret < 0))
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- return -EIO;
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+ if (unlikely(ret < 0)) {
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+ retval = -EIO;
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+ goto exit;
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+ }
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- ret = lan78xx_wait_eeprom(dev);
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- if (ret < 0)
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- return ret;
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+ retval = lan78xx_wait_eeprom(dev);
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+ if (retval < 0)
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+ goto exit;
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ret = lan78xx_read_reg(dev, E2P_DATA, &val);
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- if (unlikely(ret < 0))
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- return -EIO;
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+ if (unlikely(ret < 0)) {
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+ retval = -EIO;
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+ goto exit;
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+ }
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data[i] = val & 0xFF;
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offset++;
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}
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- return 0;
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+ retval = 0;
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+exit:
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+ if ((dev->devid & ID_REV_CHIP_ID_MASK_) == 0x78000000)
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+ ret = lan78xx_write_reg(dev, HW_CFG, saved);
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+
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+ return retval;
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}
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static int lan78xx_read_eeprom(struct lan78xx_net *dev, u32 offset,
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@@ -509,44 +530,67 @@ static int lan78xx_write_raw_eeprom(struct lan78xx_net *dev, u32 offset,
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u32 length, u8 *data)
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{
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u32 val;
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+ u32 saved;
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int i, ret;
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+ int retval;
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- ret = lan78xx_eeprom_confirm_not_busy(dev);
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- if (ret)
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- return ret;
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+ /* depends on chip, some EEPROM pins are muxed with LED function.
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+ * disable & restore LED function to access EEPROM.
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+ */
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+ ret = lan78xx_read_reg(dev, HW_CFG, &val);
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+ saved = val;
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+ if ((dev->devid & ID_REV_CHIP_ID_MASK_) == 0x78000000) {
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+ val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
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+ ret = lan78xx_write_reg(dev, HW_CFG, val);
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+ }
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+
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+ retval = lan78xx_eeprom_confirm_not_busy(dev);
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+ if (retval)
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+ goto exit;
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/* Issue write/erase enable command */
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val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_;
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ret = lan78xx_write_reg(dev, E2P_CMD, val);
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- if (unlikely(ret < 0))
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- return -EIO;
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+ if (unlikely(ret < 0)) {
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+ retval = -EIO;
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+ goto exit;
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+ }
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- ret = lan78xx_wait_eeprom(dev);
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- if (ret < 0)
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- return ret;
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+ retval = lan78xx_wait_eeprom(dev);
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+ if (retval < 0)
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+ goto exit;
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for (i = 0; i < length; i++) {
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/* Fill data register */
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val = data[i];
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ret = lan78xx_write_reg(dev, E2P_DATA, val);
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- if (ret < 0)
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- return ret;
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+ if (ret < 0) {
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+ retval = -EIO;
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+ goto exit;
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+ }
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/* Send "write" command */
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val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_;
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val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
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ret = lan78xx_write_reg(dev, E2P_CMD, val);
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- if (ret < 0)
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- return ret;
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+ if (ret < 0) {
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+ retval = -EIO;
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+ goto exit;
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+ }
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- ret = lan78xx_wait_eeprom(dev);
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- if (ret < 0)
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- return ret;
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+ retval = lan78xx_wait_eeprom(dev);
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+ if (retval < 0)
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+ goto exit;
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offset++;
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}
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- return 0;
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+ retval = 0;
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+exit:
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+ if ((dev->devid & ID_REV_CHIP_ID_MASK_) == 0x78000000)
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+ ret = lan78xx_write_reg(dev, HW_CFG, saved);
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+
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+ return retval;
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}
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static int lan78xx_read_raw_otp(struct lan78xx_net *dev, u32 offset,
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