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@@ -1090,7 +1090,7 @@ static void tsi721_init_pc2sr_mapping(struct tsi721_device *priv)
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* from rstart to lstart.
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*/
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static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
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- u64 rstart, u32 size, u32 flags)
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+ u64 rstart, u64 size, u32 flags)
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{
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struct tsi721_device *priv = mport->priv;
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int i, avail = -1;
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@@ -1103,6 +1103,10 @@ static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
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struct tsi721_ib_win_mapping *map = NULL;
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int ret = -EBUSY;
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+ /* Max IBW size supported by HW is 16GB */
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+ if (size > 0x400000000UL)
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+ return -EINVAL;
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+
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if (direct) {
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/* Calculate minimal acceptable window size and base address */
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@@ -1110,15 +1114,15 @@ static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
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ibw_start = lstart & ~(ibw_size - 1);
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tsi_debug(IBW, &priv->pdev->dev,
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- "Direct (RIO_0x%llx -> PCIe_%pad), size=0x%x, ibw_start = 0x%llx",
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+ "Direct (RIO_0x%llx -> PCIe_%pad), size=0x%llx, ibw_start = 0x%llx",
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rstart, &lstart, size, ibw_start);
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while ((lstart + size) > (ibw_start + ibw_size)) {
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ibw_size *= 2;
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ibw_start = lstart & ~(ibw_size - 1);
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- if (ibw_size > 0x80000000) { /* Limit max size to 2GB */
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+ /* Check for crossing IBW max size 16GB */
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+ if (ibw_size > 0x400000000UL)
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return -EBUSY;
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- }
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}
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loc_start = ibw_start;
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@@ -1129,7 +1133,7 @@ static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
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} else {
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tsi_debug(IBW, &priv->pdev->dev,
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- "Translated (RIO_0x%llx -> PCIe_%pad), size=0x%x",
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+ "Translated (RIO_0x%llx -> PCIe_%pad), size=0x%llx",
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rstart, &lstart, size);
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if (!is_power_of_2(size) || size < 0x1000 ||
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