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@@ -4650,20 +4650,26 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
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return -EINVAL;
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- tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
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- PP_ASSERT_WITH_CODE(!tmp_result,
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- "Failed to freeze SCLK MCLK DPM!",
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- result = tmp_result);
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+ if (smum_is_dpm_running(hwmgr)) {
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+ if (!data->sclk_dpm_key_disabled)
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+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
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+
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+ if (!data->mclk_dpm_key_disabled)
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+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
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+ }
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tmp_result = smum_populate_requested_graphic_levels(hwmgr, request);
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PP_ASSERT_WITH_CODE(!tmp_result,
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"Failed to populate requested graphic levels!",
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result = tmp_result);
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- tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
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- PP_ASSERT_WITH_CODE(!tmp_result,
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- "Failed to unfreeze SCLK MCLK DPM!",
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- result = tmp_result);
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+ if (smum_is_dpm_running(hwmgr)) {
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+ if (!data->sclk_dpm_key_disabled)
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+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
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+
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+ if (!data->mclk_dpm_key_disabled)
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+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
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+ }
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smu7_find_min_clock_masks(hwmgr, &sclk_mask, &mclk_mask,
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request->min_sclk, request->min_mclk);
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