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@@ -49,6 +49,7 @@
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#define PLL_USER_CTL_U 0x14
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#define PLL_CONFIG_CTL 0x18
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+#define PLL_CONFIG_CTL_U 0x20
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#define PLL_TEST_CTL 0x1c
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#define PLL_TEST_CTL_U 0x20
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#define PLL_STATUS 0x24
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@@ -106,6 +107,36 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
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#define wait_for_pll_offline(pll) \
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wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
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+void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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+ const struct alpha_pll_config *config)
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+{
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+ u32 val, mask;
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+ u32 off = pll->offset;
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+
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+ regmap_write(regmap, off + PLL_L_VAL, config->l);
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+ regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
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+ regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
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+ regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
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+
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+ val = config->main_output_mask;
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+ val |= config->aux_output_mask;
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+ val |= config->aux2_output_mask;
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+ val |= config->early_output_mask;
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+ val |= config->pre_div_val;
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+ val |= config->post_div_val;
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+ val |= config->vco_val;
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+
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+ mask = config->main_output_mask;
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+ mask |= config->aux_output_mask;
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+ mask |= config->aux2_output_mask;
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+ mask |= config->early_output_mask;
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+ mask |= config->pre_div_mask;
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+ mask |= config->post_div_mask;
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+ mask |= config->vco_mask;
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+
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+ regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val);
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+}
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+
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static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
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{
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int ret;
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