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@@ -53,8 +53,7 @@
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#define checkuart(rp, rv, lhu, bit, uart) \
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/* Load address of CLK_RST register */ \
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- movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \
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- movt rp, #TEGRA_CLK_RST_DEVICES_##lhu >> 16 ; \
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+ ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
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/* Load value from CLK_RST register */ \
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ldr rp, [rp, #0] ; \
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/* Test UART's reset bit */ \
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@@ -62,8 +61,7 @@
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/* If set, can't use UART; jump to save no UART */ \
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bne 90f ; \
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/* Load address of CLK_OUT_ENB register */ \
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- movw rp, #TEGRA_CLK_OUT_ENB_##lhu & 0xffff ; \
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- movt rp, #TEGRA_CLK_OUT_ENB_##lhu >> 16 ; \
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+ ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
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/* Load value from CLK_OUT_ENB register */ \
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ldr rp, [rp, #0] ; \
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/* Test UART's clock enable bit */ \
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@@ -71,8 +69,7 @@
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/* If clear, can't use UART; jump to save no UART */ \
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beq 90f ; \
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/* Passed all tests, load address of UART registers */ \
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- movw rp, #TEGRA_UART##uart##_BASE & 0xffff ; \
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- movt rp, #TEGRA_UART##uart##_BASE >> 16 ; \
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+ ldr rp, =TEGRA_UART##uart##_BASE ; \
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/* Jump to save UART address */ \
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b 91f
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@@ -90,15 +87,16 @@
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#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
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/* Check ODMDATA */
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-10: movw \rp, #TEGRA_PMC_SCRATCH20 & 0xffff
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- movt \rp, #TEGRA_PMC_SCRATCH20 >> 16
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+10: ldr \rp, =TEGRA_PMC_SCRATCH20
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ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
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- ubfx \rv, \rp, #18, #2 @ 19:18 are console type
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+ lsr \rv, \rp, #18 @ 19:18 are console type
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+ and \rv, \rv, #3
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cmp \rv, #2 @ 2 and 3 mean DCC, UART
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beq 11f @ some boards swap the meaning
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cmp \rv, #3 @ so accept either
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bne 90f
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-11: ubfx \rv, \rp, #15, #3 @ 17:15 are UART ID
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+11: lsr \rv, \rp, #15 @ 17:15 are UART ID
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+ and \rv, #7
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cmp \rv, #0 @ UART 0?
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beq 20f
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cmp \rv, #1 @ UART 1?
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