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@@ -84,13 +84,22 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K |
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IWL_PRPH_SCRATCH_MTR_MODE |
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(IWL_PRPH_MTR_FORMAT_256B &
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- IWL_PRPH_SCRATCH_MTR_FORMAT);
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+ IWL_PRPH_SCRATCH_MTR_FORMAT) |
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+ IWL_PRPH_SCRATCH_EARLY_DEBUG_EN |
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+ IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
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prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
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/* initialize RX default queue */
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prph_sc_ctrl->rbd_cfg.free_rbd_addr =
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cpu_to_le64(trans_pcie->rxq->bd_dma);
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+ /* Configure debug, for integration */
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+ iwl_pcie_alloc_fw_monitor(trans, 0);
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+ prph_sc_ctrl->hwm_cfg.hwm_base_addr =
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+ cpu_to_le64(trans_pcie->fw_mon_phys);
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+ prph_sc_ctrl->hwm_cfg.hwm_size =
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+ cpu_to_le32(trans_pcie->fw_mon_size);
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+
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
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if (ret) {
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@@ -157,10 +166,6 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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iwl_enable_interrupts(trans);
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- /* Configure debug, if exists */
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- if (trans->dbg_dest_tlv)
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- iwl_pcie_apply_destination(trans);
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-
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/* kick FW self load */
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iwl_write64(trans, CSR_CTXT_INFO_ADDR,
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trans_pcie->ctxt_info_dma_addr);
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