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@@ -75,6 +75,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9887_HW_1_0_VERSION,
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.id = QCA9887_HW_1_0_VERSION,
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@@ -99,6 +102,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA6174_HW_2_1_VERSION,
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.id = QCA6174_HW_2_1_VERSION,
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@@ -122,6 +128,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA6174_HW_2_1_VERSION,
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.id = QCA6174_HW_2_1_VERSION,
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@@ -145,6 +154,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA6174_HW_3_0_VERSION,
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.id = QCA6174_HW_3_0_VERSION,
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@@ -168,6 +180,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA6174_HW_3_2_VERSION,
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.id = QCA6174_HW_3_2_VERSION,
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@@ -194,6 +209,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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.id = QCA99X0_HW_2_0_DEV_VERSION,
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@@ -223,6 +241,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 11,
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.n_cipher_suites = 11,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9984_HW_1_0_DEV_VERSION,
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.id = QCA9984_HW_1_0_DEV_VERSION,
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@@ -257,6 +278,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 1560,
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.vht160_mcs_rx_highest = 1560,
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.vht160_mcs_tx_highest = 1560,
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.vht160_mcs_tx_highest = 1560,
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.n_cipher_suites = 11,
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.n_cipher_suites = 11,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9888_HW_2_0_DEV_VERSION,
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.id = QCA9888_HW_2_0_DEV_VERSION,
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@@ -290,6 +314,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 780,
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.vht160_mcs_rx_highest = 780,
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.vht160_mcs_tx_highest = 780,
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.vht160_mcs_tx_highest = 780,
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.n_cipher_suites = 11,
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.n_cipher_suites = 11,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9377_HW_1_0_DEV_VERSION,
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.id = QCA9377_HW_1_0_DEV_VERSION,
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@@ -313,6 +340,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA9377_HW_1_1_DEV_VERSION,
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.id = QCA9377_HW_1_1_DEV_VERSION,
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@@ -338,6 +368,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 8,
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.n_cipher_suites = 8,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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{
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{
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.id = QCA4019_HW_1_0_DEV_VERSION,
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.id = QCA4019_HW_1_0_DEV_VERSION,
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@@ -368,6 +401,9 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_rx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.vht160_mcs_tx_highest = 0,
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.n_cipher_suites = 11,
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.n_cipher_suites = 11,
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+ .num_peers = TARGET_TLV_NUM_PEERS,
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+ .ast_skid_limit = 0x10,
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+ .num_wds_entries = 0x20,
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},
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},
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};
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};
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