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@@ -29,7 +29,7 @@
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/* 10 (register bit affects spdif_in and spdif_out) */
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/* 10 (register bit affects spdif_in and spdif_out) */
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#define TEGRA124_CLK_I2S1 11
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#define TEGRA124_CLK_I2S1 11
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#define TEGRA124_CLK_I2C1 12
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#define TEGRA124_CLK_I2C1 12
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-#define TEGRA124_CLK_NDFLASH 13
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+/* 13 */
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#define TEGRA124_CLK_SDMMC1 14
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#define TEGRA124_CLK_SDMMC1 14
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#define TEGRA124_CLK_SDMMC4 15
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#define TEGRA124_CLK_SDMMC4 15
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/* 16 */
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/* 16 */
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@@ -83,7 +83,7 @@
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/* 64 */
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/* 64 */
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#define TEGRA124_CLK_UARTD 65
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#define TEGRA124_CLK_UARTD 65
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-#define TEGRA124_CLK_UARTE 66
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+/* 66 */
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#define TEGRA124_CLK_I2C3 67
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#define TEGRA124_CLK_I2C3 67
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#define TEGRA124_CLK_SBC4 68
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#define TEGRA124_CLK_SBC4 68
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#define TEGRA124_CLK_SDMMC3 69
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#define TEGRA124_CLK_SDMMC3 69
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@@ -97,7 +97,7 @@
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#define TEGRA124_CLK_TRACE 77
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#define TEGRA124_CLK_TRACE 77
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#define TEGRA124_CLK_SOC_THERM 78
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#define TEGRA124_CLK_SOC_THERM 78
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#define TEGRA124_CLK_DTV 79
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#define TEGRA124_CLK_DTV 79
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-#define TEGRA124_CLK_NDSPEED 80
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+/* 80 */
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#define TEGRA124_CLK_I2CSLOW 81
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#define TEGRA124_CLK_I2CSLOW 81
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#define TEGRA124_CLK_DSIB 82
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#define TEGRA124_CLK_DSIB 82
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#define TEGRA124_CLK_TSEC 83
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#define TEGRA124_CLK_TSEC 83
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