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@@ -1780,7 +1780,7 @@ enum i915_power_well_id {
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#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4))
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#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4))
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#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \
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- (ln * (_CNL_PORT_TX_DW4_LN1_AE - \
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+ ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
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_CNL_PORT_TX_DW4_LN0_AE)))
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#define _ICL_PORT_TX_DW4_GRP_A 0x162690
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#define _ICL_PORT_TX_DW4_GRP_B 0x6C690
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@@ -1793,8 +1793,8 @@ enum i915_power_well_id {
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#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_PORT(port, \
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_ICL_PORT_TX_DW4_LN0_A, \
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_ICL_PORT_TX_DW4_LN0_B) + \
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- (ln * (_ICL_PORT_TX_DW4_LN1_A - \
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- _ICL_PORT_TX_DW4_LN0_A)))
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+ ((ln) * (_ICL_PORT_TX_DW4_LN1_A - \
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+ _ICL_PORT_TX_DW4_LN0_A)))
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#define LOADGEN_SELECT (1 << 31)
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#define POST_CURSOR_1(x) ((x) << 12)
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#define POST_CURSOR_1_MASK (0x3F << 12)
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@@ -6076,8 +6076,8 @@ enum {
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/* Display/Sprite base address macros */
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#define DISP_BASEADDR_MASK (0xfffff000)
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-#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
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-#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
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+#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
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+#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
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/*
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* VBIOS flags
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@@ -7091,7 +7091,7 @@ enum {
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#define GEN11_VECS(x) (31 - (x))
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#define GEN11_VCS(x) (x)
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-#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + (x * 4))
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+#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
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#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
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#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
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@@ -7100,12 +7100,12 @@ enum {
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#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
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#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
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-#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + (x * 4))
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+#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
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#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
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#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
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-#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + (x * 4))
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+#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
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#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
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#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
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@@ -7497,15 +7497,15 @@ enum {
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#define _PCH_DPLL_A 0xc6014
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#define _PCH_DPLL_B 0xc6018
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-#define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
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+#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
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#define _PCH_FPA0 0xc6040
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#define FP_CB_TUNE (0x3 << 22)
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#define _PCH_FPA1 0xc6044
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#define _PCH_FPB0 0xc6048
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#define _PCH_FPB1 0xc604c
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-#define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
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-#define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
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+#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
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+#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
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#define PCH_DPLL_TEST _MMIO(0xc606c)
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@@ -8337,11 +8337,11 @@ enum {
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#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
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#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
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#define GEN7_PARITY_ERROR_ROW(reg) \
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- ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
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+ (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
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#define GEN7_PARITY_ERROR_BANK(reg) \
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- ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
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+ (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
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#define GEN7_PARITY_ERROR_SUBBANK(reg) \
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- ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
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+ (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
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#define GEN7_L3CDERRST1_ENABLE (1 << 7)
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#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
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@@ -8614,7 +8614,7 @@ enum skl_power_gate {
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#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
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#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
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#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
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-#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + h * 4))
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+#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4))
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#define HDCP_SHA_TEXT _MMIO(0x66d18)
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/* HDCP Auth Registers */
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@@ -8630,7 +8630,7 @@ enum skl_power_gate {
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_PORTC_HDCP_AUTHENC, \
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_PORTD_HDCP_AUTHENC, \
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_PORTE_HDCP_AUTHENC, \
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- _PORTF_HDCP_AUTHENC) + x)
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+ _PORTF_HDCP_AUTHENC) + (x))
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#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
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#define HDCP_CONF_CAPTURE_AN BIT(0)
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#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
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@@ -8651,7 +8651,7 @@ enum skl_power_gate {
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#define HDCP_STATUS_R0_READY BIT(18)
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#define HDCP_STATUS_AN_READY BIT(17)
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#define HDCP_STATUS_CIPHER BIT(16)
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-#define HDCP_STATUS_FRAME_CNT(x) ((x >> 8) & 0xff)
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+#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff)
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/* Per-pipe DDI Function Control */
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#define _TRANS_DDI_FUNC_CTL_A 0x60400
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@@ -9402,7 +9402,7 @@ enum skl_power_gate {
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_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
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BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
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#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
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- ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
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+ (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
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/* RX upper control divider to select actual RX clock output from 8x */
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#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
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#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
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@@ -9415,7 +9415,7 @@ enum skl_power_gate {
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_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
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BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
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#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
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- ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
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+ (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
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/* 8/3X divider to select the actual 8/3X clock output from 8x */
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#define BXT_MIPI1_8X_BY3_SHIFT 19
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#define BXT_MIPI2_8X_BY3_SHIFT 3
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@@ -9428,7 +9428,7 @@ enum skl_power_gate {
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_MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
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BXT_MIPI2_8X_BY3_DIVIDER_MASK)
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#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
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- ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
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+ (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
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/* RX lower control divider to select actual RX clock output from 8x */
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#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
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#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
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@@ -9441,7 +9441,7 @@ enum skl_power_gate {
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_MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
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BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
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#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
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- ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
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+ (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
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#define RX_DIVIDER_BIT_1_2 0x3
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#define RX_DIVIDER_BIT_3_4 0xC
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Paulo Zanoni