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@@ -31,10 +31,14 @@
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#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
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#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
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-static void wakeup_secondary(void)
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+static void __iomem *backupram;
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+
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+static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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- static void __iomem *backupram;
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+ static void __iomem *scu_base;
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+ unsigned int ncores;
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+ int i;
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np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
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if (!np) {
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@@ -48,29 +52,6 @@ static void wakeup_secondary(void)
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return;
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}
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- /*
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- * write the address of secondary startup into the backup ram register
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- * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
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- * backup ram register at offset 0x1FF0, which is what boot rom code
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- * is waiting for. This will wake up the secondary core from WFE.
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- */
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- writel(virt_to_phys(secondary_startup),
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- backupram + UX500_CPU1_JUMPADDR_OFFSET);
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- writel(0xA1FEED01,
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- backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
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-
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- /* make sure write buffer is drained */
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- mb();
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- iounmap(backupram);
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-}
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-
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-static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
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-{
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- struct device_node *np;
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- static void __iomem *scu_base;
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- unsigned int ncores;
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- int i;
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-
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (!np) {
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pr_err("No SCU base address\n");
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@@ -92,7 +73,19 @@ static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
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static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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- wakeup_secondary();
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+ /*
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+ * write the address of secondary startup into the backup ram register
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+ * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
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+ * backup ram register at offset 0x1FF0, which is what boot rom code
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+ * is waiting for. This will wake up the secondary core from WFE.
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+ */
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+ writel(virt_to_phys(secondary_startup),
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+ backupram + UX500_CPU1_JUMPADDR_OFFSET);
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+ writel(0xA1FEED01,
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+ backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
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+
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+ /* make sure write buffer is drained */
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+ mb();
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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