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@@ -39,9 +39,6 @@
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/* Delay in usec */
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#define PCI_RESET_DELAY_US 3000000
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-#define cfg_dbg(fmt...) do { } while(0)
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-//#define cfg_dbg(fmt...) printk(fmt)
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-
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#ifdef CONFIG_PCI_MSI
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int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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@@ -402,8 +399,8 @@ static void pnv_pci_config_check_eeh(struct pci_dn *pdn)
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}
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}
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- cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
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- (pdn->busno << 8) | (pdn->devfn), pe_no, fstate);
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+ pr_devel(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
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+ (pdn->busno << 8) | (pdn->devfn), pe_no, fstate);
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/* Clear the frozen state if applicable */
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if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE ||
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@@ -451,8 +448,8 @@ int pnv_pci_cfg_read(struct pci_dn *pdn,
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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- cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
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- __func__, pdn->busno, pdn->devfn, where, size, *val);
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+ pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
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+ __func__, pdn->busno, pdn->devfn, where, size, *val);
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return PCIBIOS_SUCCESSFUL;
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}
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@@ -462,8 +459,8 @@ int pnv_pci_cfg_write(struct pci_dn *pdn,
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struct pnv_phb *phb = pdn->phb->private_data;
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u32 bdfn = (pdn->busno << 8) | pdn->devfn;
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- cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
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- pdn->busno, pdn->devfn, where, size, val);
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+ pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
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+ __func__, pdn->busno, pdn->devfn, where, size, val);
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switch (size) {
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case 1:
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opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
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