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@@ -62,21 +62,9 @@
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#define CFG_ENABLE_PM_MSG_FWD BIT(1)
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#define CFG_ENABLE_PM_MSG_FWD BIT(1)
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#define CFG_ENABLE_INT_MSG_FWD BIT(2)
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#define CFG_ENABLE_INT_MSG_FWD BIT(2)
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#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
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#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
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-#define CFG_ENABLE_SLT_MSG_FWD BIT(5)
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-#define CFG_ENABLE_VEN_MSG_FWD BIT(7)
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-#define CFG_ENABLE_OTH_MSG_FWD BIT(13)
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-#define CFG_ENABLE_VEN_MSG_EN BIT(14)
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-#define CFG_ENABLE_VEN_MSG_VEN_INV BIT(15)
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-#define CFG_ENABLE_VEN_MSG_VEN_ID GENMASK(31, 16)
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#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
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#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
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CFG_ENABLE_INT_MSG_FWD | \
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CFG_ENABLE_INT_MSG_FWD | \
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- CFG_ENABLE_ERR_MSG_FWD | \
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- CFG_ENABLE_SLT_MSG_FWD | \
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- CFG_ENABLE_VEN_MSG_FWD | \
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- CFG_ENABLE_OTH_MSG_FWD | \
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- CFG_ENABLE_VEN_MSG_EN | \
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- CFG_ENABLE_VEN_MSG_VEN_INV | \
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- CFG_ENABLE_VEN_MSG_VEN_ID)
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+ CFG_ENABLE_ERR_MSG_FWD)
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/* Misc interrupt status mask bits */
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/* Misc interrupt status mask bits */
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#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
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#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
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