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@@ -582,7 +582,7 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
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* divided-down version of it.
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*/
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/* m1 is reserved as 0 in Pineview, n is a ring counter */
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-static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
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+static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
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{
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clock->m = clock->m2 + 2;
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clock->p = clock->p1 * clock->p2;
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@@ -599,7 +599,7 @@ static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
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return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
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}
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-static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
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+static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
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{
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clock->m = i9xx_dpll_compute_m(clock);
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clock->p = clock->p1 * clock->p2;
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@@ -611,7 +611,7 @@ static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
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return clock->dot;
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}
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-static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
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+static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
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{
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clock->m = clock->m1 * clock->m2;
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clock->p = clock->p1 * clock->p2;
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@@ -623,7 +623,7 @@ static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
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return clock->dot / 5;
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}
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-int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
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+int chv_calc_dpll_params(int refclk, struct dpll *clock)
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{
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clock->m = clock->m1 * clock->m2;
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clock->p = clock->p1 * clock->p2;
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@@ -644,7 +644,7 @@ int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
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static bool intel_PLL_is_valid(struct drm_device *dev,
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const intel_limit_t *limit,
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- const intel_clock_t *clock)
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+ const struct dpll *clock)
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{
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if (clock->n < limit->n.min || limit->n.max < clock->n)
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INTELPllInvalid("n out of range\n");
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@@ -716,11 +716,11 @@ i9xx_select_p2_div(const intel_limit_t *limit,
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static bool
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i9xx_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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- int target, int refclk, intel_clock_t *match_clock,
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- intel_clock_t *best_clock)
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+ int target, int refclk, struct dpll *match_clock,
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+ struct dpll *best_clock)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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- intel_clock_t clock;
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+ struct dpll clock;
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int err = target;
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memset(best_clock, 0, sizeof(*best_clock));
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@@ -773,11 +773,11 @@ i9xx_find_best_dpll(const intel_limit_t *limit,
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static bool
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pnv_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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- int target, int refclk, intel_clock_t *match_clock,
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- intel_clock_t *best_clock)
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+ int target, int refclk, struct dpll *match_clock,
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+ struct dpll *best_clock)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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- intel_clock_t clock;
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+ struct dpll clock;
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int err = target;
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memset(best_clock, 0, sizeof(*best_clock));
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@@ -828,11 +828,11 @@ pnv_find_best_dpll(const intel_limit_t *limit,
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static bool
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g4x_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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- int target, int refclk, intel_clock_t *match_clock,
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- intel_clock_t *best_clock)
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+ int target, int refclk, struct dpll *match_clock,
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+ struct dpll *best_clock)
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{
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struct drm_device *dev = crtc_state->base.crtc->dev;
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- intel_clock_t clock;
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+ struct dpll clock;
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int max_n;
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bool found = false;
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/* approximately equals target * 0.00585 */
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@@ -878,8 +878,8 @@ g4x_find_best_dpll(const intel_limit_t *limit,
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* best configuration and error found so far. Return the calculated error.
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*/
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static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
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- const intel_clock_t *calculated_clock,
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- const intel_clock_t *best_clock,
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+ const struct dpll *calculated_clock,
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+ const struct dpll *best_clock,
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unsigned int best_error_ppm,
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unsigned int *error_ppm)
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{
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@@ -921,12 +921,12 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
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static bool
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vlv_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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- int target, int refclk, intel_clock_t *match_clock,
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- intel_clock_t *best_clock)
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+ int target, int refclk, struct dpll *match_clock,
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+ struct dpll *best_clock)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_device *dev = crtc->base.dev;
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- intel_clock_t clock;
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+ struct dpll clock;
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unsigned int bestppm = 1000000;
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/* min update 19.2 MHz */
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int max_n = min(limit->n.max, refclk / 19200);
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@@ -980,13 +980,13 @@ vlv_find_best_dpll(const intel_limit_t *limit,
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static bool
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chv_find_best_dpll(const intel_limit_t *limit,
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struct intel_crtc_state *crtc_state,
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- int target, int refclk, intel_clock_t *match_clock,
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- intel_clock_t *best_clock)
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+ int target, int refclk, struct dpll *match_clock,
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+ struct dpll *best_clock)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_device *dev = crtc->base.dev;
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unsigned int best_error_ppm;
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- intel_clock_t clock;
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+ struct dpll clock;
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uint64_t m2;
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int found = false;
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@@ -1036,7 +1036,7 @@ chv_find_best_dpll(const intel_limit_t *limit,
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}
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bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
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- intel_clock_t *best_clock)
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+ struct dpll *best_clock)
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{
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int refclk = 100000;
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const intel_limit_t *limit = &intel_limits_bxt;
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@@ -7057,7 +7057,7 @@ static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
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static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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- intel_clock_t *reduced_clock)
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+ struct dpll *reduced_clock)
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{
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struct drm_device *dev = crtc->base.dev;
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u32 fp, fp2 = 0;
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@@ -7481,7 +7481,7 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
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static void i9xx_compute_dpll(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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- intel_clock_t *reduced_clock)
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+ struct dpll *reduced_clock)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -7557,7 +7557,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
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static void i8xx_compute_dpll(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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- intel_clock_t *reduced_clock)
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+ struct dpll *reduced_clock)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -8028,7 +8028,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = pipe_config->cpu_transcoder;
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- intel_clock_t clock;
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+ struct dpll clock;
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u32 mdiv;
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int refclk = 100000;
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@@ -8125,7 +8125,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = pipe_config->cpu_transcoder;
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enum dpio_channel port = vlv_pipe_to_channel(pipe);
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- intel_clock_t clock;
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+ struct dpll clock;
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u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
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int refclk = 100000;
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@@ -8788,7 +8788,7 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
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static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state,
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- intel_clock_t *reduced_clock)
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+ struct dpll *reduced_clock)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct drm_device *dev = crtc->dev;
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@@ -8896,7 +8896,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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- intel_clock_t reduced_clock;
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+ struct dpll reduced_clock;
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bool has_reduced_clock = false;
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struct intel_shared_dpll *pll;
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const intel_limit_t *limit;
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@@ -10626,7 +10626,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
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int pipe = pipe_config->cpu_transcoder;
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u32 dpll = pipe_config->dpll_hw_state.dpll;
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u32 fp;
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- intel_clock_t clock;
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+ struct dpll clock;
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int port_clock;
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int refclk = i9xx_pll_refclk(dev, pipe_config);
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