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@@ -112,6 +112,9 @@
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#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
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#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
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+/* Tegra CPU clock and reset control regs */
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+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
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+
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static void __iomem *clk_base;
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static void __iomem *pmc_base;
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@@ -1283,6 +1286,27 @@ static void __init tegra124_pll_init(void __iomem *clk_base,
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}
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+/* Tegra124 CPU clock and reset control functions */
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+static void tegra124_wait_cpu_in_reset(u32 cpu)
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+{
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+ unsigned int reg;
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+
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+ do {
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+ reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
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+ cpu_relax();
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+ } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
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+}
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+
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+static void tegra124_disable_cpu_clock(u32 cpu)
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+{
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+ /* flow controller would take care in the power sequence. */
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+}
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+
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+static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
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+ .wait_for_reset = tegra124_wait_cpu_in_reset,
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+ .disable_clock = tegra124_disable_cpu_clock,
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+};
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+
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static const struct of_device_id pmc_match[] __initconst = {
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{ .compatible = "nvidia,tegra124-pmc" },
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{},
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@@ -1366,5 +1390,7 @@ static void __init tegra124_clock_init(struct device_node *np)
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tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
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tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
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+
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+ tegra_cpu_car_ops = &tegra124_cpu_car_ops;
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}
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CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
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