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@@ -17,6 +17,7 @@
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#define CLKID_I2C 22
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#define CLKID_I2C 22
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#define CLKID_SAR_ADC 23
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#define CLKID_SAR_ADC 23
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#define CLKID_RNG0 25
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#define CLKID_RNG0 25
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+#define CLKID_UART0 26
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#define CLKID_SPI 34
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#define CLKID_SPI 34
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#define CLKID_ETH 36
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#define CLKID_ETH 36
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#define CLKID_AIU_GLUE 38
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#define CLKID_AIU_GLUE 38
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@@ -24,12 +25,14 @@
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#define CLKID_I2S_OUT 40
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#define CLKID_I2S_OUT 40
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#define CLKID_MIXER_IFACE 44
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#define CLKID_MIXER_IFACE 44
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#define CLKID_AIU 47
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#define CLKID_AIU 47
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+#define CLKID_UART1 48
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#define CLKID_USB0 50
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB1 51
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#define CLKID_USB 55
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#define CLKID_USB 55
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#define CLKID_HDMI_PCLK 63
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#define CLKID_HDMI_PCLK 63
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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#define CLKID_USB0_DDR_BRIDGE 65
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+#define CLKID_UART2 68
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#define CLKID_SANA 69
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#define CLKID_SANA 69
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_GCLK_VENCI_INT0 77
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#define CLKID_AOCLK_GATE 80
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#define CLKID_AOCLK_GATE 80
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