|
@@ -241,6 +241,17 @@ int pxa_irq_to_gpio(int irq)
|
|
|
return irq_gpio0;
|
|
|
}
|
|
|
|
|
|
+static bool pxa_gpio_has_pinctrl(void)
|
|
|
+{
|
|
|
+ switch (gpio_type) {
|
|
|
+ case PXA3XX_GPIO:
|
|
|
+ return false;
|
|
|
+
|
|
|
+ default:
|
|
|
+ return true;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|
|
{
|
|
|
struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
|
|
@@ -255,9 +266,11 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
|
|
unsigned long flags;
|
|
|
int ret;
|
|
|
|
|
|
- ret = pinctrl_gpio_direction_input(chip->base + offset);
|
|
|
- if (!ret)
|
|
|
- return 0;
|
|
|
+ if (pxa_gpio_has_pinctrl()) {
|
|
|
+ ret = pinctrl_gpio_direction_input(chip->base + offset);
|
|
|
+ if (!ret)
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
|
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
|
|
|
@@ -282,9 +295,11 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip,
|
|
|
|
|
|
writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
|
|
|
|
|
|
- ret = pinctrl_gpio_direction_output(chip->base + offset);
|
|
|
- if (ret)
|
|
|
- return ret;
|
|
|
+ if (pxa_gpio_has_pinctrl()) {
|
|
|
+ ret = pinctrl_gpio_direction_output(chip->base + offset);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
|
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
|
|
|
@@ -348,8 +363,12 @@ static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
|
|
|
pchip->chip.set = pxa_gpio_set;
|
|
|
pchip->chip.to_irq = pxa_gpio_to_irq;
|
|
|
pchip->chip.ngpio = ngpio;
|
|
|
- pchip->chip.request = gpiochip_generic_request;
|
|
|
- pchip->chip.free = gpiochip_generic_free;
|
|
|
+
|
|
|
+ if (pxa_gpio_has_pinctrl()) {
|
|
|
+ pchip->chip.request = gpiochip_generic_request;
|
|
|
+ pchip->chip.free = gpiochip_generic_free;
|
|
|
+ }
|
|
|
+
|
|
|
#ifdef CONFIG_OF_GPIO
|
|
|
pchip->chip.of_node = np;
|
|
|
pchip->chip.of_xlate = pxa_gpio_of_xlate;
|