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@@ -52,6 +52,15 @@
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_VOP 122
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#define SCLK_HDMI_HDCP 123
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+#define SCLK_MAC_SRC 124
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+#define SCLK_MAC_EXTCLK 125
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+#define SCLK_MAC 126
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+#define SCLK_MAC_REFOUT 127
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+#define SCLK_MAC_REF 128
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+#define SCLK_MAC_RX 129
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+#define SCLK_MAC_TX 130
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+#define SCLK_MAC_PHY 131
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+#define SCLK_MAC_OUT 132
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/* dclk gates */
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#define DCLK_VOP 190
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@@ -61,6 +70,7 @@
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#define ACLK_DMAC 194
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#define ACLK_PERI 210
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#define ACLK_VOP 211
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+#define ACLK_GMAC 212
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/* pclk gates */
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#define PCLK_GPIO0 320
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@@ -82,8 +92,13 @@
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#define PCLK_PERI 363
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#define PCLK_HDMI_CTRL 364
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#define PCLK_HDMI_PHY 365
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+#define PCLK_GMAC 367
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/* hclk gates */
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+#define HCLK_I2S0_8CH 442
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+#define HCLK_I2S1_8CH 443
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+#define HCLK_I2S2_2CH 444
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+#define HCLK_SPDIF_8CH 445
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#define HCLK_VOP 452
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#define HCLK_NANDC 453
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#define HCLK_SDMMC 456
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Heiko Stuebner