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@@ -82,19 +82,6 @@ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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#define NR_GIC_CPU_IF 8
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static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
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-/*
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- * Supported arch specific GIC irq extension.
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- * Default make them NULL.
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- */
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-struct irq_chip gic_arch_extn = {
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- .irq_eoi = NULL,
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- .irq_mask = NULL,
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- .irq_unmask = NULL,
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- .irq_retrigger = NULL,
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- .irq_set_type = NULL,
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- .irq_set_wake = NULL,
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-};
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-
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#ifndef MAX_GIC_NR
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#define MAX_GIC_NR 1
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#endif
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@@ -167,34 +154,16 @@ static int gic_peek_irq(struct irq_data *d, u32 offset)
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static void gic_mask_irq(struct irq_data *d)
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{
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- unsigned long flags;
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-
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- raw_spin_lock_irqsave(&irq_controller_lock, flags);
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gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
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- if (gic_arch_extn.irq_mask)
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- gic_arch_extn.irq_mask(d);
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- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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- unsigned long flags;
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-
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- raw_spin_lock_irqsave(&irq_controller_lock, flags);
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- if (gic_arch_extn.irq_unmask)
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- gic_arch_extn.irq_unmask(d);
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gic_poke_irq(d, GIC_DIST_ENABLE_SET);
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- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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}
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static void gic_eoi_irq(struct irq_data *d)
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{
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- if (gic_arch_extn.irq_eoi) {
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- raw_spin_lock(&irq_controller_lock);
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- gic_arch_extn.irq_eoi(d);
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- raw_spin_unlock(&irq_controller_lock);
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- }
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-
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writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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}
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@@ -251,8 +220,6 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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void __iomem *base = gic_dist_base(d);
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unsigned int gicirq = gic_irq(d);
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- unsigned long flags;
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- int ret;
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/* Interrupt configuration for SGIs can't be changed */
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if (gicirq < 16)
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@@ -263,25 +230,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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- raw_spin_lock_irqsave(&irq_controller_lock, flags);
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-
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- if (gic_arch_extn.irq_set_type)
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- gic_arch_extn.irq_set_type(d, type);
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-
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- ret = gic_configure_irq(gicirq, type, base, NULL);
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-
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- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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-
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- return ret;
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-}
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-
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-static int gic_retrigger(struct irq_data *d)
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-{
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- if (gic_arch_extn.irq_retrigger)
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- return gic_arch_extn.irq_retrigger(d);
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-
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- /* the genirq layer expects 0 if we can't retrigger in hardware */
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- return 0;
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+ return gic_configure_irq(gicirq, type, base, NULL);
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}
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#ifdef CONFIG_SMP
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@@ -312,21 +261,6 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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}
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#endif
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-#ifdef CONFIG_PM
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-static int gic_set_wake(struct irq_data *d, unsigned int on)
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-{
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- int ret = -ENXIO;
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-
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- if (gic_arch_extn.irq_set_wake)
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- ret = gic_arch_extn.irq_set_wake(d, on);
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-
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- return ret;
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-}
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-
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-#else
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-#define gic_set_wake NULL
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-#endif
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-
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static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
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{
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u32 irqstat, irqnr;
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@@ -385,11 +319,9 @@ static struct irq_chip gic_chip = {
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoi_irq,
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.irq_set_type = gic_set_type,
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- .irq_retrigger = gic_retrigger,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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- .irq_set_wake = gic_set_wake,
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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};
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@@ -1055,7 +987,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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set_handle_irq(gic_handle_irq);
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}
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- gic_chip.flags |= gic_arch_extn.flags;
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gic_dist_init(gic);
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gic_cpu_init(gic);
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gic_pm_init(gic);
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