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@@ -280,6 +280,15 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
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goto free;
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goto free;
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}
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}
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+ /**
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+ * The IOMMU bit defines the upper limit of the GPU-addressable space.
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+ * This will be refined in nouveau_ttm_init but we need to do it early
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+ * for instmem to behave properly
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+ */
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+ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(tdev->func->iommu_bit));
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+ if (ret)
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+ goto free;
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+
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nvkm_device_tegra_probe_iommu(tdev);
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nvkm_device_tegra_probe_iommu(tdev);
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ret = nvkm_device_tegra_power_up(tdev);
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ret = nvkm_device_tegra_power_up(tdev);
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