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@@ -668,9 +668,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_TM)
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mr r31, r4
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addi r3, r31, VCPU_FPRS_TM
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- bl .load_fp_state
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+ bl load_fp_state
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addi r3, r31, VCPU_VRS_TM
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- bl .load_vr_state
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+ bl load_vr_state
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mr r4, r31
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lwz r7, VCPU_VRSAVE_TM(r4)
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mtspr SPRN_VRSAVE, r7
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@@ -1414,9 +1414,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_TM)
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/* Save FP/VSX. */
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addi r3, r9, VCPU_FPRS_TM
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- bl .store_fp_state
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+ bl store_fp_state
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addi r3, r9, VCPU_VRS_TM
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- bl .store_vr_state
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+ bl store_vr_state
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mfspr r6, SPRN_VRSAVE
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stw r6, VCPU_VRSAVE_TM(r9)
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1:
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@@ -2430,11 +2430,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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mtmsrd r8
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isync
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addi r3,r3,VCPU_FPRS
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- bl .store_fp_state
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+ bl store_fp_state
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#ifdef CONFIG_ALTIVEC
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BEGIN_FTR_SECTION
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addi r3,r31,VCPU_VRS
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- bl .store_vr_state
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+ bl store_vr_state
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif
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mfspr r6,SPRN_VRSAVE
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@@ -2466,11 +2466,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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mtmsrd r8
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isync
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addi r3,r4,VCPU_FPRS
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- bl .load_fp_state
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+ bl load_fp_state
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#ifdef CONFIG_ALTIVEC
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BEGIN_FTR_SECTION
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addi r3,r31,VCPU_VRS
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- bl .load_vr_state
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+ bl load_vr_state
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif
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lwz r7,VCPU_VRSAVE(r31)
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