|
@@ -344,12 +344,16 @@ enum OpalMveEnableAction {
|
|
OPAL_ENABLE_MVE = 1
|
|
OPAL_ENABLE_MVE = 1
|
|
};
|
|
};
|
|
|
|
|
|
-enum OpalPciResetAndReinitScope {
|
|
|
|
|
|
+enum OpalPciResetScope {
|
|
OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
|
|
OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
|
|
OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
|
|
OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
|
|
OPAL_PCI_IODA_TABLE_RESET = 6,
|
|
OPAL_PCI_IODA_TABLE_RESET = 6,
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+enum OpalPciReinitScope {
|
|
|
|
+ OPAL_REINIT_PCI_DEV = 1000
|
|
|
|
+};
|
|
|
|
+
|
|
enum OpalPciResetState {
|
|
enum OpalPciResetState {
|
|
OPAL_DEASSERT_RESET = 0,
|
|
OPAL_DEASSERT_RESET = 0,
|
|
OPAL_ASSERT_RESET = 1
|
|
OPAL_ASSERT_RESET = 1
|
|
@@ -801,7 +805,7 @@ int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
|
|
int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
|
|
int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
|
|
uint64_t diag_buffer_len);
|
|
uint64_t diag_buffer_len);
|
|
int64_t opal_pci_fence_phb(uint64_t phb_id);
|
|
int64_t opal_pci_fence_phb(uint64_t phb_id);
|
|
-int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
|
|
|
|
|
|
+int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
|
|
int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
|
|
int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
|
|
int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
|
|
int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
|
|
int64_t opal_get_epow_status(__be64 *status);
|
|
int64_t opal_get_epow_status(__be64 *status);
|