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@@ -35,6 +35,9 @@
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/* STM32F7 I2C registers */
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#define STM32F7_I2C_CR1 0x00
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#define STM32F7_I2C_CR2 0x04
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+#define STM32F7_I2C_OAR1 0x08
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+#define STM32F7_I2C_OAR2 0x0C
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+#define STM32F7_I2C_PECR 0x20
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#define STM32F7_I2C_TIMINGR 0x10
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#define STM32F7_I2C_ISR 0x18
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#define STM32F7_I2C_ICR 0x1C
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@@ -42,6 +45,10 @@
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#define STM32F7_I2C_TXDR 0x28
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/* STM32F7 I2C control 1 */
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+#define STM32F7_I2C_CR1_PECEN BIT(23)
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+#define STM32F7_I2C_CR1_SBC BIT(16)
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+#define STM32F7_I2C_CR1_RXDMAEN BIT(15)
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+#define STM32F7_I2C_CR1_TXDMAEN BIT(14)
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#define STM32F7_I2C_CR1_ANFOFF BIT(12)
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#define STM32F7_I2C_CR1_ERRIE BIT(7)
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#define STM32F7_I2C_CR1_TCIE BIT(6)
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@@ -57,34 +64,77 @@
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| STM32F7_I2C_CR1_NACKIE \
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| STM32F7_I2C_CR1_RXIE \
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| STM32F7_I2C_CR1_TXIE)
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+#define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
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+ | STM32F7_I2C_CR1_STOPIE \
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+ | STM32F7_I2C_CR1_NACKIE \
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+ | STM32F7_I2C_CR1_RXIE \
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+ | STM32F7_I2C_CR1_TXIE)
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/* STM32F7 I2C control 2 */
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+#define STM32F7_I2C_CR2_PECBYTE BIT(26)
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#define STM32F7_I2C_CR2_RELOAD BIT(24)
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#define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
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#define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
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#define STM32F7_I2C_CR2_NACK BIT(15)
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#define STM32F7_I2C_CR2_STOP BIT(14)
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#define STM32F7_I2C_CR2_START BIT(13)
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+#define STM32F7_I2C_CR2_HEAD10R BIT(12)
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+#define STM32F7_I2C_CR2_ADD10 BIT(11)
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#define STM32F7_I2C_CR2_RD_WRN BIT(10)
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+#define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
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+#define STM32F7_I2C_CR2_SADD10(n) (((n) & \
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+ STM32F7_I2C_CR2_SADD10_MASK))
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#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
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#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
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+/* STM32F7 I2C Own Address 1 */
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+#define STM32F7_I2C_OAR1_OA1EN BIT(15)
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+#define STM32F7_I2C_OAR1_OA1MODE BIT(10)
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+#define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
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+#define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
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+ STM32F7_I2C_OAR1_OA1_10_MASK))
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+#define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
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+#define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
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+#define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
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+ | STM32F7_I2C_OAR1_OA1_10_MASK \
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+ | STM32F7_I2C_OAR1_OA1EN \
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+ | STM32F7_I2C_OAR1_OA1MODE)
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+
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+/* STM32F7 I2C Own Address 2 */
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+#define STM32F7_I2C_OAR2_OA2EN BIT(15)
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+#define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
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+#define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
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+#define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
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+#define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
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+#define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
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+ | STM32F7_I2C_OAR2_OA2_7_MASK \
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+ | STM32F7_I2C_OAR2_OA2EN)
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+
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/* STM32F7 I2C Interrupt Status */
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+#define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
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+#define STM32F7_I2C_ISR_ADDCODE_GET(n) \
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+ (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
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+#define STM32F7_I2C_ISR_DIR BIT(16)
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#define STM32F7_I2C_ISR_BUSY BIT(15)
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+#define STM32F7_I2C_ISR_PECERR BIT(11)
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#define STM32F7_I2C_ISR_ARLO BIT(9)
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#define STM32F7_I2C_ISR_BERR BIT(8)
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#define STM32F7_I2C_ISR_TCR BIT(7)
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#define STM32F7_I2C_ISR_TC BIT(6)
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#define STM32F7_I2C_ISR_STOPF BIT(5)
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#define STM32F7_I2C_ISR_NACKF BIT(4)
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+#define STM32F7_I2C_ISR_ADDR BIT(3)
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#define STM32F7_I2C_ISR_RXNE BIT(2)
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#define STM32F7_I2C_ISR_TXIS BIT(1)
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+#define STM32F7_I2C_ISR_TXE BIT(0)
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/* STM32F7 I2C Interrupt Clear */
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+#define STM32F7_I2C_ICR_PECCF BIT(11)
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#define STM32F7_I2C_ICR_ARLOCF BIT(9)
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#define STM32F7_I2C_ICR_BERRCF BIT(8)
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#define STM32F7_I2C_ICR_STOPCF BIT(5)
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#define STM32F7_I2C_ICR_NACKCF BIT(4)
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+#define STM32F7_I2C_ICR_ADDRCF BIT(3)
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/* STM32F7 I2C Timing */
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#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
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@@ -94,6 +144,8 @@
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#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
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#define STM32F7_I2C_MAX_LEN 0xff
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+#define STM32F7_I2C_DMA_LEN_MIN 0x16
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+#define STM32F7_I2C_MAX_SLAVE 0x2
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#define STM32F7_I2C_DNF_DEFAULT 0
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#define STM32F7_I2C_DNF_MAX 16
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@@ -159,11 +211,12 @@ struct stm32f7_i2c_setup {
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/**
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* struct stm32f7_i2c_timings - private I2C output parameters
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- * @prec: Prescaler value
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+ * @node: List entry
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+ * @presc: Prescaler value
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* @scldel: Data setup time
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* @sdadel: Data hold time
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* @sclh: SCL high period (master mode)
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- * @sclh: SCL low period (master mode)
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+ * @scll: SCL low period (master mode)
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*/
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struct stm32f7_i2c_timings {
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struct list_head node;
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@@ -176,18 +229,30 @@ struct stm32f7_i2c_timings {
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/**
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* struct stm32f7_i2c_msg - client specific data
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- * @addr: 8-bit slave addr, including r/w bit
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+ * @addr: 8-bit or 10-bit slave addr, including r/w bit
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* @count: number of bytes to be transferred
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* @buf: data buffer
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* @result: result of the transfer
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* @stop: last I2C msg to be sent, i.e. STOP to be generated
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+ * @smbus: boolean to know if the I2C IP is used in SMBus mode
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+ * @size: type of SMBus protocol
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+ * @read_write: direction of SMBus protocol
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+ * SMBus block read and SMBus block write - block read process call protocols
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+ * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
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+ * contain a maximum of 32 bytes of data + byte command + byte count + PEC
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+ * This buffer has to be 32-bit aligned to be compliant with memory address
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+ * register in DMA mode.
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*/
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struct stm32f7_i2c_msg {
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- u8 addr;
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+ u16 addr;
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u32 count;
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u8 *buf;
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int result;
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bool stop;
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+ bool smbus;
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+ int size;
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+ char read_write;
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+ u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
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};
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/**
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@@ -204,6 +269,13 @@ struct stm32f7_i2c_msg {
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* @f7_msg: customized i2c msg for driver usage
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* @setup: I2C timing input setup
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* @timing: I2C computed timings
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+ * @slave: list of slave devices registered on the I2C bus
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+ * @slave_running: slave device currently used
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+ * @slave_dir: transfer direction for the current slave device
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+ * @master_mode: boolean to know in which mode the I2C is running (master or
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+ * slave)
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+ * @dma: dma data
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+ * @use_dma: boolean to know if dma is used in the current transfer
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*/
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struct stm32f7_i2c_dev {
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struct i2c_adapter adap;
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@@ -218,6 +290,12 @@ struct stm32f7_i2c_dev {
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struct stm32f7_i2c_msg f7_msg;
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struct stm32f7_i2c_setup setup;
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struct stm32f7_i2c_timings timing;
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+ struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
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+ struct i2c_client *slave_running;
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+ u32 slave_dir;
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+ bool master_mode;
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+ struct stm32_i2c_dma *dma;
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+ bool use_dma;
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};
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/**
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@@ -283,6 +361,11 @@ static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
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writel_relaxed(readl_relaxed(reg) & ~mask, reg);
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}
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+static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
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+{
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+ stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
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+}
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+
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static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
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struct stm32f7_i2c_setup *setup,
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struct stm32f7_i2c_timings *output)
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@@ -524,6 +607,25 @@ static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
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return 0;
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}
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+static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
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+{
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+ void __iomem *base = i2c_dev->base;
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+ u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
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+
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+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
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+}
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+
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+static void stm32f7_i2c_dma_callback(void *arg)
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+{
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+ struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
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+ struct stm32_i2c_dma *dma = i2c_dev->dma;
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+ struct device *dev = dma->chan_using->device->dev;
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+
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+ stm32f7_i2c_disable_dma_req(i2c_dev);
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+ dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
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+ complete(&dma->dma_complete);
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+}
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+
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static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
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{
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struct stm32f7_i2c_timings *t = &i2c_dev->timing;
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@@ -567,6 +669,9 @@ static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
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if (f7_msg->count) {
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*f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
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f7_msg->count--;
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+ } else {
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+ /* Flush RX buffer has no data is expected */
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+ readb_relaxed(base + STM32F7_I2C_RXDR);
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}
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}
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@@ -575,6 +680,9 @@ static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
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struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
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u32 cr2;
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+ if (i2c_dev->use_dma)
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+ f7_msg->count -= STM32F7_I2C_MAX_LEN;
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+
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cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
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cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
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@@ -588,6 +696,43 @@ static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
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writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
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}
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+static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
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+{
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+ struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
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+ u32 cr2;
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+ u8 *val;
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+
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+ /*
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+ * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
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+ * data received inform us how many data will follow.
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+ */
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+ stm32f7_i2c_read_rx_data(i2c_dev);
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+
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+ /*
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+ * Update NBYTES with the value read to continue the transfer
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+ */
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+ val = f7_msg->buf - sizeof(u8);
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+ f7_msg->count = *val;
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+ cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
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+ cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
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+ cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
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+ writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
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+}
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+
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+static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
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+{
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+ struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
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+
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+ dev_info(i2c_dev->dev, "Trying to recover bus\n");
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+
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+ stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
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+ STM32F7_I2C_CR1_PE);
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+
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+ stm32f7_i2c_hw_config(i2c_dev);
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+
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+ return 0;
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+}
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+
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static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
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{
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u32 status;
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@@ -597,12 +742,18 @@ static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
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status,
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!(status & STM32F7_I2C_ISR_BUSY),
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10, 1000);
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+ if (!ret)
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+ return 0;
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+
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+ dev_info(i2c_dev->dev, "bus busy\n");
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+
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+ ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
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if (ret) {
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- dev_dbg(i2c_dev->dev, "bus busy\n");
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- ret = -EBUSY;
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+ dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
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+ return ret;
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}
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- return ret;
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+ return -EBUSY;
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}
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static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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@@ -611,6 +762,7 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
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void __iomem *base = i2c_dev->base;
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u32 cr1, cr2;
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+ int ret;
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f7_msg->addr = msg->addr;
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f7_msg->buf = msg->buf;
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@@ -629,8 +781,15 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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cr2 |= STM32F7_I2C_CR2_RD_WRN;
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/* Set slave address */
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- cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
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- cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
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+ cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
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+ if (msg->flags & I2C_M_TEN) {
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+ cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
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+ cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
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+ cr2 |= STM32F7_I2C_CR2_ADD10;
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+ } else {
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+ cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
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+ cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
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+ }
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/* Set nb bytes to transfer and reload if needed */
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cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
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@@ -645,16 +804,286 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
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STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
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- /* Clear TX/RX interrupt */
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+ /* Clear DMA req and TX/RX interrupt */
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+ cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
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+ STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
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+
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+ /* Configure DMA or enable RX/TX interrupt */
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+ i2c_dev->use_dma = false;
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+ if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
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+ ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
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+ msg->flags & I2C_M_RD,
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+ f7_msg->count, f7_msg->buf,
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+ stm32f7_i2c_dma_callback,
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+ i2c_dev);
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+ if (!ret)
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+ i2c_dev->use_dma = true;
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+ else
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+ dev_warn(i2c_dev->dev, "can't use DMA\n");
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+ }
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+
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+ if (!i2c_dev->use_dma) {
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+ if (msg->flags & I2C_M_RD)
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+ cr1 |= STM32F7_I2C_CR1_RXIE;
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+ else
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+ cr1 |= STM32F7_I2C_CR1_TXIE;
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+ } else {
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+ if (msg->flags & I2C_M_RD)
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+ cr1 |= STM32F7_I2C_CR1_RXDMAEN;
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+ else
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+ cr1 |= STM32F7_I2C_CR1_TXDMAEN;
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+ }
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+
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+ /* Configure Start/Repeated Start */
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+ cr2 |= STM32F7_I2C_CR2_START;
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+
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+ i2c_dev->master_mode = true;
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+
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+ /* Write configurations registers */
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+ writel_relaxed(cr1, base + STM32F7_I2C_CR1);
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+ writel_relaxed(cr2, base + STM32F7_I2C_CR2);
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+}
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+
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+static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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+ unsigned short flags, u8 command,
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+ union i2c_smbus_data *data)
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+{
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+ struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
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+ struct device *dev = i2c_dev->dev;
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+ void __iomem *base = i2c_dev->base;
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+ u32 cr1, cr2;
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+ int i, ret;
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+
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+ f7_msg->result = 0;
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+ reinit_completion(&i2c_dev->complete);
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+
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+ cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
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+ cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
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+
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+ /* Set transfer direction */
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+ cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
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+ if (f7_msg->read_write)
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+ cr2 |= STM32F7_I2C_CR2_RD_WRN;
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+
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+ /* Set slave address */
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+ cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
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+ cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
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+
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+ f7_msg->smbus_buf[0] = command;
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+ switch (f7_msg->size) {
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+ case I2C_SMBUS_QUICK:
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+ f7_msg->stop = true;
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+ f7_msg->count = 0;
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+ break;
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+ case I2C_SMBUS_BYTE:
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+ f7_msg->stop = true;
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+ f7_msg->count = 1;
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+ break;
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+ case I2C_SMBUS_BYTE_DATA:
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+ if (f7_msg->read_write) {
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+ f7_msg->stop = false;
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+ f7_msg->count = 1;
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+ cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
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+ } else {
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+ f7_msg->stop = true;
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+ f7_msg->count = 2;
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+ f7_msg->smbus_buf[1] = data->byte;
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+ }
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+ break;
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+ case I2C_SMBUS_WORD_DATA:
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+ if (f7_msg->read_write) {
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+ f7_msg->stop = false;
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+ f7_msg->count = 1;
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+ cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
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+ } else {
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+ f7_msg->stop = true;
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+ f7_msg->count = 3;
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+ f7_msg->smbus_buf[1] = data->word & 0xff;
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+ f7_msg->smbus_buf[2] = data->word >> 8;
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+ }
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+ break;
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+ case I2C_SMBUS_BLOCK_DATA:
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+ if (f7_msg->read_write) {
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+ f7_msg->stop = false;
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+ f7_msg->count = 1;
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+ cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
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+ } else {
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+ f7_msg->stop = true;
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+ if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
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+ !data->block[0]) {
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+ dev_err(dev, "Invalid block write size %d\n",
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+ data->block[0]);
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+ return -EINVAL;
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+ }
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+ f7_msg->count = data->block[0] + 2;
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+ for (i = 1; i < f7_msg->count; i++)
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+ f7_msg->smbus_buf[i] = data->block[i - 1];
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+ }
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+ break;
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+ case I2C_SMBUS_PROC_CALL:
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+ f7_msg->stop = false;
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+ f7_msg->count = 3;
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+ f7_msg->smbus_buf[1] = data->word & 0xff;
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+ f7_msg->smbus_buf[2] = data->word >> 8;
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+ cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
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+ f7_msg->read_write = I2C_SMBUS_READ;
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+ break;
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+ case I2C_SMBUS_BLOCK_PROC_CALL:
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+ f7_msg->stop = false;
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+ if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
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+ dev_err(dev, "Invalid block write size %d\n",
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+ data->block[0]);
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+ return -EINVAL;
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+ }
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+ f7_msg->count = data->block[0] + 2;
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+ for (i = 1; i < f7_msg->count; i++)
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+ f7_msg->smbus_buf[i] = data->block[i - 1];
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+ cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
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+ f7_msg->read_write = I2C_SMBUS_READ;
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+ break;
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+ default:
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+ dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
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+ return -EOPNOTSUPP;
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+ }
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+
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+ f7_msg->buf = f7_msg->smbus_buf;
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+
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+ /* Configure PEC */
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+ if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
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+ cr1 |= STM32F7_I2C_CR1_PECEN;
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+ cr2 |= STM32F7_I2C_CR2_PECBYTE;
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+ if (!f7_msg->read_write)
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+ f7_msg->count++;
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+ } else {
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+ cr1 &= ~STM32F7_I2C_CR1_PECEN;
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+ cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
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+ }
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+
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+ /* Set number of bytes to be transferred */
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+ cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
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+ cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
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+
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+ /* Enable NACK, STOP, error and transfer complete interrupts */
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+ cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
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+ STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
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+
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+ /* Clear DMA req and TX/RX interrupt */
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+ cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
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+ STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
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+
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+ /* Configure DMA or enable RX/TX interrupt */
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+ i2c_dev->use_dma = false;
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+ if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
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+ ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
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+ cr2 & STM32F7_I2C_CR2_RD_WRN,
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+ f7_msg->count, f7_msg->buf,
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+ stm32f7_i2c_dma_callback,
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+ i2c_dev);
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+ if (!ret)
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+ i2c_dev->use_dma = true;
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+ else
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+ dev_warn(i2c_dev->dev, "can't use DMA\n");
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+ }
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+
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+ if (!i2c_dev->use_dma) {
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+ if (cr2 & STM32F7_I2C_CR2_RD_WRN)
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+ cr1 |= STM32F7_I2C_CR1_RXIE;
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+ else
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+ cr1 |= STM32F7_I2C_CR1_TXIE;
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+ } else {
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+ if (cr2 & STM32F7_I2C_CR2_RD_WRN)
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+ cr1 |= STM32F7_I2C_CR1_RXDMAEN;
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+ else
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+ cr1 |= STM32F7_I2C_CR1_TXDMAEN;
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+ }
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+
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+ /* Set Start bit */
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+ cr2 |= STM32F7_I2C_CR2_START;
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+
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+ i2c_dev->master_mode = true;
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+
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+ /* Write configurations registers */
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+ writel_relaxed(cr1, base + STM32F7_I2C_CR1);
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+ writel_relaxed(cr2, base + STM32F7_I2C_CR2);
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+
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+ return 0;
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+}
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+
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+static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
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+{
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+ struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
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+ void __iomem *base = i2c_dev->base;
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+ u32 cr1, cr2;
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+ int ret;
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+
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+ cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
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+ cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
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+
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+ /* Set transfer direction */
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+ cr2 |= STM32F7_I2C_CR2_RD_WRN;
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+
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+ switch (f7_msg->size) {
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+ case I2C_SMBUS_BYTE_DATA:
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+ f7_msg->count = 1;
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+ break;
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+ case I2C_SMBUS_WORD_DATA:
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+ case I2C_SMBUS_PROC_CALL:
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+ f7_msg->count = 2;
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+ break;
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+ case I2C_SMBUS_BLOCK_DATA:
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+ case I2C_SMBUS_BLOCK_PROC_CALL:
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+ f7_msg->count = 1;
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+ cr2 |= STM32F7_I2C_CR2_RELOAD;
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+ break;
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+ }
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+
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+ f7_msg->buf = f7_msg->smbus_buf;
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+ f7_msg->stop = true;
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+
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+ /* Add one byte for PEC if needed */
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+ if (cr1 & STM32F7_I2C_CR1_PECEN)
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+ f7_msg->count++;
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+
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+ /* Set number of bytes to be transferred */
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+ cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
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+ cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
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+
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+ /*
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+ * Configure RX/TX interrupt:
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+ */
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cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
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+ cr1 |= STM32F7_I2C_CR1_RXIE;
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- /* Enable RX/TX interrupt according to msg direction */
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- if (msg->flags & I2C_M_RD)
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+ /*
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+ * Configure DMA or enable RX/TX interrupt:
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+ * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
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+ * dma as we don't know in advance how many data will be received
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+ */
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+ cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
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+ STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
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+
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+ i2c_dev->use_dma = false;
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+ if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
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+ f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
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+ f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
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+ ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
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+ cr2 & STM32F7_I2C_CR2_RD_WRN,
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+ f7_msg->count, f7_msg->buf,
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+ stm32f7_i2c_dma_callback,
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+ i2c_dev);
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+
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+ if (!ret)
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+ i2c_dev->use_dma = true;
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+ else
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+ dev_warn(i2c_dev->dev, "can't use DMA\n");
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+ }
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+
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+ if (!i2c_dev->use_dma)
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cr1 |= STM32F7_I2C_CR1_RXIE;
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else
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- cr1 |= STM32F7_I2C_CR1_TXIE;
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+ cr1 |= STM32F7_I2C_CR1_RXDMAEN;
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- /* Configure Start/Repeated Start */
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+ /* Configure Repeated Start */
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cr2 |= STM32F7_I2C_CR2_START;
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/* Write configurations registers */
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@@ -662,9 +1091,278 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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writel_relaxed(cr2, base + STM32F7_I2C_CR2);
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}
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-static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
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+static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
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{
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- stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
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+ struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
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+ u8 count, internal_pec, received_pec;
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+
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+ internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
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+
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+ switch (f7_msg->size) {
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+ case I2C_SMBUS_BYTE:
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+ case I2C_SMBUS_BYTE_DATA:
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+ received_pec = f7_msg->smbus_buf[1];
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+ break;
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+ case I2C_SMBUS_WORD_DATA:
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+ case I2C_SMBUS_PROC_CALL:
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+ received_pec = f7_msg->smbus_buf[2];
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+ break;
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+ case I2C_SMBUS_BLOCK_DATA:
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+ case I2C_SMBUS_BLOCK_PROC_CALL:
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+ count = f7_msg->smbus_buf[0];
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|
|
+ received_pec = f7_msg->smbus_buf[count];
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (internal_pec != received_pec) {
|
|
|
+ dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
|
|
|
+ internal_pec, received_pec);
|
|
|
+ return -EBADMSG;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
|
|
|
+{
|
|
|
+ u32 addr;
|
|
|
+
|
|
|
+ if (!slave)
|
|
|
+ return false;
|
|
|
+
|
|
|
+ if (slave->flags & I2C_CLIENT_TEN) {
|
|
|
+ /*
|
|
|
+ * For 10-bit addr, addcode = 11110XY with
|
|
|
+ * X = Bit 9 of slave address
|
|
|
+ * Y = Bit 8 of slave address
|
|
|
+ */
|
|
|
+ addr = slave->addr >> 8;
|
|
|
+ addr |= 0x78;
|
|
|
+ if (addr == addcode)
|
|
|
+ return true;
|
|
|
+ } else {
|
|
|
+ addr = slave->addr & 0x7f;
|
|
|
+ if (addr == addcode)
|
|
|
+ return true;
|
|
|
+ }
|
|
|
+
|
|
|
+ return false;
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
|
|
|
+{
|
|
|
+ struct i2c_client *slave = i2c_dev->slave_running;
|
|
|
+ void __iomem *base = i2c_dev->base;
|
|
|
+ u32 mask;
|
|
|
+ u8 value = 0;
|
|
|
+
|
|
|
+ if (i2c_dev->slave_dir) {
|
|
|
+ /* Notify i2c slave that new read transfer is starting */
|
|
|
+ i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Disable slave TX config in case of I2C combined message
|
|
|
+ * (I2C Write followed by I2C Read)
|
|
|
+ */
|
|
|
+ mask = STM32F7_I2C_CR2_RELOAD;
|
|
|
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
|
|
|
+ mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
|
|
|
+ STM32F7_I2C_CR1_TCIE;
|
|
|
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
|
|
|
+
|
|
|
+ /* Enable TX empty, STOP, NACK interrupts */
|
|
|
+ mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
|
|
|
+ STM32F7_I2C_CR1_TXIE;
|
|
|
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
|
|
|
+
|
|
|
+ } else {
|
|
|
+ /* Notify i2c slave that new write transfer is starting */
|
|
|
+ i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
|
|
|
+
|
|
|
+ /* Set reload mode to be able to ACK/NACK each received byte */
|
|
|
+ mask = STM32F7_I2C_CR2_RELOAD;
|
|
|
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Set STOP, NACK, RX empty and transfer complete interrupts.*
|
|
|
+ * Set Slave Byte Control to be able to ACK/NACK each data
|
|
|
+ * byte received
|
|
|
+ */
|
|
|
+ mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
|
|
|
+ STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
|
|
|
+ STM32F7_I2C_CR1_TCIE;
|
|
|
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
|
|
|
+{
|
|
|
+ void __iomem *base = i2c_dev->base;
|
|
|
+ u32 isr, addcode, dir, mask;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
|
|
+ addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
|
|
|
+ dir = isr & STM32F7_I2C_ISR_DIR;
|
|
|
+
|
|
|
+ for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
|
|
|
+ if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
|
|
|
+ i2c_dev->slave_running = i2c_dev->slave[i];
|
|
|
+ i2c_dev->slave_dir = dir;
|
|
|
+
|
|
|
+ /* Start I2C slave processing */
|
|
|
+ stm32f7_i2c_slave_start(i2c_dev);
|
|
|
+
|
|
|
+ /* Clear ADDR flag */
|
|
|
+ mask = STM32F7_I2C_ICR_ADDRCF;
|
|
|
+ writel_relaxed(mask, base + STM32F7_I2C_ICR);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
|
|
|
+ struct i2c_client *slave, int *id)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
|
|
|
+ if (i2c_dev->slave[i] == slave) {
|
|
|
+ *id = i;
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
|
|
|
+
|
|
|
+ return -ENODEV;
|
|
|
+}
|
|
|
+
|
|
|
+static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
|
|
|
+ struct i2c_client *slave, int *id)
|
|
|
+{
|
|
|
+ struct device *dev = i2c_dev->dev;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * slave[0] supports 7-bit and 10-bit slave address
|
|
|
+ * slave[1] supports 7-bit slave address only
|
|
|
+ */
|
|
|
+ for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
|
|
|
+ if (i == 1 && (slave->flags & I2C_CLIENT_PEC))
|
|
|
+ continue;
|
|
|
+ if (!i2c_dev->slave[i]) {
|
|
|
+ *id = i;
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
|
|
|
+
|
|
|
+ return -EINVAL;
|
|
|
+}
|
|
|
+
|
|
|
+static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
|
|
|
+ if (i2c_dev->slave[i])
|
|
|
+ return true;
|
|
|
+ }
|
|
|
+
|
|
|
+ return false;
|
|
|
+}
|
|
|
+
|
|
|
+static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
|
|
|
+{
|
|
|
+ int i, busy;
|
|
|
+
|
|
|
+ busy = 0;
|
|
|
+ for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
|
|
|
+ if (i2c_dev->slave[i])
|
|
|
+ busy++;
|
|
|
+ }
|
|
|
+
|
|
|
+ return i == busy;
|
|
|
+}
|
|
|
+
|
|
|
+static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
|
|
|
+{
|
|
|
+ void __iomem *base = i2c_dev->base;
|
|
|
+ u32 cr2, status, mask;
|
|
|
+ u8 val;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
|
|
+
|
|
|
+ /* Slave transmitter mode */
|
|
|
+ if (status & STM32F7_I2C_ISR_TXIS) {
|
|
|
+ i2c_slave_event(i2c_dev->slave_running,
|
|
|
+ I2C_SLAVE_READ_PROCESSED,
|
|
|
+ &val);
|
|
|
+
|
|
|
+ /* Write data byte */
|
|
|
+ writel_relaxed(val, base + STM32F7_I2C_TXDR);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Transfer Complete Reload for Slave receiver mode */
|
|
|
+ if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
|
|
|
+ /*
|
|
|
+ * Read data byte then set NBYTES to receive next byte or NACK
|
|
|
+ * the current received byte
|
|
|
+ */
|
|
|
+ val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
|
|
|
+ ret = i2c_slave_event(i2c_dev->slave_running,
|
|
|
+ I2C_SLAVE_WRITE_RECEIVED,
|
|
|
+ &val);
|
|
|
+ if (!ret) {
|
|
|
+ cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
|
|
|
+ cr2 |= STM32F7_I2C_CR2_NBYTES(1);
|
|
|
+ writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
|
|
|
+ } else {
|
|
|
+ mask = STM32F7_I2C_CR2_NACK;
|
|
|
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* NACK received */
|
|
|
+ if (status & STM32F7_I2C_ISR_NACKF) {
|
|
|
+ dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
|
|
|
+ writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* STOP received */
|
|
|
+ if (status & STM32F7_I2C_ISR_STOPF) {
|
|
|
+ /* Disable interrupts */
|
|
|
+ stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
|
|
|
+
|
|
|
+ if (i2c_dev->slave_dir) {
|
|
|
+ /*
|
|
|
+ * Flush TX buffer in order to not used the byte in
|
|
|
+ * TXDR for the next transfer
|
|
|
+ */
|
|
|
+ mask = STM32F7_I2C_ISR_TXE;
|
|
|
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Clear STOP flag */
|
|
|
+ writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
|
|
|
+
|
|
|
+ /* Notify i2c slave that a STOP flag has been detected */
|
|
|
+ i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
|
|
|
+
|
|
|
+ i2c_dev->slave_running = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Address match received */
|
|
|
+ if (status & STM32F7_I2C_ISR_ADDR)
|
|
|
+ stm32f7_i2c_slave_addr(i2c_dev);
|
|
|
+
|
|
|
+ return IRQ_HANDLED;
|
|
|
}
|
|
|
|
|
|
static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
|
|
@@ -673,6 +1371,13 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
|
|
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
|
|
void __iomem *base = i2c_dev->base;
|
|
|
u32 status, mask;
|
|
|
+ int ret = IRQ_HANDLED;
|
|
|
+
|
|
|
+ /* Check if the interrupt if for a slave device */
|
|
|
+ if (!i2c_dev->master_mode) {
|
|
|
+ ret = stm32f7_i2c_slave_isr_event(i2c_dev);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
|
|
|
status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
|
|
|
|
|
@@ -694,12 +1399,21 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
|
|
/* STOP detection flag */
|
|
|
if (status & STM32F7_I2C_ISR_STOPF) {
|
|
|
/* Disable interrupts */
|
|
|
- stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
|
|
|
+ if (stm32f7_i2c_is_slave_registered(i2c_dev))
|
|
|
+ mask = STM32F7_I2C_XFER_IRQ_MASK;
|
|
|
+ else
|
|
|
+ mask = STM32F7_I2C_ALL_IRQ_MASK;
|
|
|
+ stm32f7_i2c_disable_irq(i2c_dev, mask);
|
|
|
|
|
|
/* Clear STOP flag */
|
|
|
writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
|
|
|
|
|
|
- complete(&i2c_dev->complete);
|
|
|
+ if (i2c_dev->use_dma) {
|
|
|
+ ret = IRQ_WAKE_THREAD;
|
|
|
+ } else {
|
|
|
+ i2c_dev->master_mode = false;
|
|
|
+ complete(&i2c_dev->complete);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
/* Transfer complete */
|
|
|
@@ -707,6 +1421,10 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
|
|
if (f7_msg->stop) {
|
|
|
mask = STM32F7_I2C_CR2_STOP;
|
|
|
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
|
|
|
+ } else if (i2c_dev->use_dma) {
|
|
|
+ ret = IRQ_WAKE_THREAD;
|
|
|
+ } else if (f7_msg->smbus) {
|
|
|
+ stm32f7_i2c_smbus_rep_start(i2c_dev);
|
|
|
} else {
|
|
|
i2c_dev->msg_id++;
|
|
|
i2c_dev->msg++;
|
|
|
@@ -714,13 +1432,50 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
+ if (status & STM32F7_I2C_ISR_TCR) {
|
|
|
+ if (f7_msg->smbus)
|
|
|
+ stm32f7_i2c_smbus_reload(i2c_dev);
|
|
|
+ else
|
|
|
+ stm32f7_i2c_reload(i2c_dev);
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
|
|
|
+{
|
|
|
+ struct stm32f7_i2c_dev *i2c_dev = data;
|
|
|
+ struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
|
|
+ struct stm32_i2c_dma *dma = i2c_dev->dma;
|
|
|
+ u32 status;
|
|
|
+ int ret;
|
|
|
+
|
|
|
/*
|
|
|
- * Transfer Complete Reload: 255 data bytes have been transferred
|
|
|
- * We have to prepare the I2C controller to transfer the remaining
|
|
|
- * data.
|
|
|
+ * Wait for dma transfer completion before sending next message or
|
|
|
+ * notity the end of xfer to the client
|
|
|
*/
|
|
|
- if (status & STM32F7_I2C_ISR_TCR)
|
|
|
- stm32f7_i2c_reload(i2c_dev);
|
|
|
+ ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
|
|
|
+ if (!ret) {
|
|
|
+ dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
|
|
|
+ stm32f7_i2c_disable_dma_req(i2c_dev);
|
|
|
+ dmaengine_terminate_all(dma->chan_using);
|
|
|
+ f7_msg->result = -ETIMEDOUT;
|
|
|
+ }
|
|
|
+
|
|
|
+ status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
|
|
+
|
|
|
+ if (status & STM32F7_I2C_ISR_TC) {
|
|
|
+ if (f7_msg->smbus) {
|
|
|
+ stm32f7_i2c_smbus_rep_start(i2c_dev);
|
|
|
+ } else {
|
|
|
+ i2c_dev->msg_id++;
|
|
|
+ i2c_dev->msg++;
|
|
|
+ stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ i2c_dev->master_mode = false;
|
|
|
+ complete(&i2c_dev->complete);
|
|
|
+ }
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
}
|
|
|
@@ -731,7 +1486,8 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
|
|
|
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
|
|
void __iomem *base = i2c_dev->base;
|
|
|
struct device *dev = i2c_dev->dev;
|
|
|
- u32 status;
|
|
|
+ struct stm32_i2c_dma *dma = i2c_dev->dma;
|
|
|
+ u32 mask, status;
|
|
|
|
|
|
status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
|
|
|
|
|
@@ -739,6 +1495,7 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
|
|
|
if (status & STM32F7_I2C_ISR_BERR) {
|
|
|
dev_err(dev, "<%s>: Bus error\n", __func__);
|
|
|
writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
|
|
|
+ stm32f7_i2c_release_bus(&i2c_dev->adap);
|
|
|
f7_msg->result = -EIO;
|
|
|
}
|
|
|
|
|
|
@@ -749,8 +1506,26 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
|
|
|
f7_msg->result = -EAGAIN;
|
|
|
}
|
|
|
|
|
|
- stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
|
|
|
+ if (status & STM32F7_I2C_ISR_PECERR) {
|
|
|
+ dev_err(dev, "<%s>: PEC error in reception\n", __func__);
|
|
|
+ writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
|
|
|
+ f7_msg->result = -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Disable interrupts */
|
|
|
+ if (stm32f7_i2c_is_slave_registered(i2c_dev))
|
|
|
+ mask = STM32F7_I2C_XFER_IRQ_MASK;
|
|
|
+ else
|
|
|
+ mask = STM32F7_I2C_ALL_IRQ_MASK;
|
|
|
+ stm32f7_i2c_disable_irq(i2c_dev, mask);
|
|
|
+
|
|
|
+ /* Disable dma */
|
|
|
+ if (i2c_dev->use_dma) {
|
|
|
+ stm32f7_i2c_disable_dma_req(i2c_dev);
|
|
|
+ dmaengine_terminate_all(dma->chan_using);
|
|
|
+ }
|
|
|
|
|
|
+ i2c_dev->master_mode = false;
|
|
|
complete(&i2c_dev->complete);
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
@@ -761,12 +1536,14 @@ static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
|
|
|
{
|
|
|
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
|
|
|
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
|
|
+ struct stm32_i2c_dma *dma = i2c_dev->dma;
|
|
|
unsigned long time_left;
|
|
|
int ret;
|
|
|
|
|
|
i2c_dev->msg = msgs;
|
|
|
i2c_dev->msg_num = num;
|
|
|
i2c_dev->msg_id = 0;
|
|
|
+ f7_msg->smbus = false;
|
|
|
|
|
|
ret = clk_enable(i2c_dev->clk);
|
|
|
if (ret) {
|
|
|
@@ -787,6 +1564,8 @@ static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
|
|
|
if (!time_left) {
|
|
|
dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
|
|
|
i2c_dev->msg->addr);
|
|
|
+ if (i2c_dev->use_dma)
|
|
|
+ dmaengine_terminate_all(dma->chan_using);
|
|
|
ret = -ETIMEDOUT;
|
|
|
}
|
|
|
|
|
|
@@ -796,14 +1575,209 @@ clk_free:
|
|
|
return (ret < 0) ? ret : num;
|
|
|
}
|
|
|
|
|
|
+static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
|
|
|
+ unsigned short flags, char read_write,
|
|
|
+ u8 command, int size,
|
|
|
+ union i2c_smbus_data *data)
|
|
|
+{
|
|
|
+ struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
|
|
|
+ struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
|
|
+ struct stm32_i2c_dma *dma = i2c_dev->dma;
|
|
|
+ struct device *dev = i2c_dev->dev;
|
|
|
+ unsigned long timeout;
|
|
|
+ int i, ret;
|
|
|
+
|
|
|
+ f7_msg->addr = addr;
|
|
|
+ f7_msg->size = size;
|
|
|
+ f7_msg->read_write = read_write;
|
|
|
+ f7_msg->smbus = true;
|
|
|
+
|
|
|
+ ret = clk_enable(i2c_dev->clk);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(i2c_dev->dev, "Failed to enable clock\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = stm32f7_i2c_wait_free_bus(i2c_dev);
|
|
|
+ if (ret)
|
|
|
+ goto clk_free;
|
|
|
+
|
|
|
+ ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
|
|
|
+ if (ret)
|
|
|
+ goto clk_free;
|
|
|
+
|
|
|
+ timeout = wait_for_completion_timeout(&i2c_dev->complete,
|
|
|
+ i2c_dev->adap.timeout);
|
|
|
+ ret = f7_msg->result;
|
|
|
+ if (ret)
|
|
|
+ goto clk_free;
|
|
|
+
|
|
|
+ if (!timeout) {
|
|
|
+ dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
|
|
|
+ if (i2c_dev->use_dma)
|
|
|
+ dmaengine_terminate_all(dma->chan_using);
|
|
|
+ ret = -ETIMEDOUT;
|
|
|
+ goto clk_free;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Check PEC */
|
|
|
+ if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
|
|
|
+ ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
|
|
|
+ if (ret)
|
|
|
+ goto clk_free;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (read_write && size != I2C_SMBUS_QUICK) {
|
|
|
+ switch (size) {
|
|
|
+ case I2C_SMBUS_BYTE:
|
|
|
+ case I2C_SMBUS_BYTE_DATA:
|
|
|
+ data->byte = f7_msg->smbus_buf[0];
|
|
|
+ break;
|
|
|
+ case I2C_SMBUS_WORD_DATA:
|
|
|
+ case I2C_SMBUS_PROC_CALL:
|
|
|
+ data->word = f7_msg->smbus_buf[0] |
|
|
|
+ (f7_msg->smbus_buf[1] << 8);
|
|
|
+ break;
|
|
|
+ case I2C_SMBUS_BLOCK_DATA:
|
|
|
+ case I2C_SMBUS_BLOCK_PROC_CALL:
|
|
|
+ for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
|
|
|
+ data->block[i] = f7_msg->smbus_buf[i];
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ dev_err(dev, "Unsupported smbus transaction\n");
|
|
|
+ ret = -EINVAL;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+clk_free:
|
|
|
+ clk_disable(i2c_dev->clk);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
|
|
|
+{
|
|
|
+ struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
|
|
|
+ void __iomem *base = i2c_dev->base;
|
|
|
+ struct device *dev = i2c_dev->dev;
|
|
|
+ u32 oar1, oar2, mask;
|
|
|
+ int id, ret;
|
|
|
+
|
|
|
+ if (slave->flags & I2C_CLIENT_PEC) {
|
|
|
+ dev_err(dev, "SMBus PEC not supported in slave mode\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
|
|
|
+ dev_err(dev, "Too much slave registered\n");
|
|
|
+ return -EBUSY;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
|
|
|
+ ret = clk_enable(i2c_dev->clk);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "Failed to enable clock\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (id == 0) {
|
|
|
+ /* Configure Own Address 1 */
|
|
|
+ oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
|
|
|
+ oar1 &= ~STM32F7_I2C_OAR1_MASK;
|
|
|
+ if (slave->flags & I2C_CLIENT_TEN) {
|
|
|
+ oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
|
|
|
+ oar1 |= STM32F7_I2C_OAR1_OA1MODE;
|
|
|
+ } else {
|
|
|
+ oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
|
|
|
+ }
|
|
|
+ oar1 |= STM32F7_I2C_OAR1_OA1EN;
|
|
|
+ i2c_dev->slave[id] = slave;
|
|
|
+ writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
|
|
|
+ } else if (id == 1) {
|
|
|
+ /* Configure Own Address 2 */
|
|
|
+ oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
|
|
|
+ oar2 &= ~STM32F7_I2C_OAR2_MASK;
|
|
|
+ if (slave->flags & I2C_CLIENT_TEN) {
|
|
|
+ ret = -EOPNOTSUPP;
|
|
|
+ goto exit;
|
|
|
+ }
|
|
|
+
|
|
|
+ oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
|
|
|
+ oar2 |= STM32F7_I2C_OAR2_OA2EN;
|
|
|
+ i2c_dev->slave[id] = slave;
|
|
|
+ writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
|
|
|
+ } else {
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto exit;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Enable ACK */
|
|
|
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
|
|
|
+
|
|
|
+ /* Enable Address match interrupt, error interrupt and enable I2C */
|
|
|
+ mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
|
|
|
+ STM32F7_I2C_CR1_PE;
|
|
|
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+exit:
|
|
|
+ if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
|
|
|
+ clk_disable(i2c_dev->clk);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
|
|
|
+{
|
|
|
+ struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
|
|
|
+ void __iomem *base = i2c_dev->base;
|
|
|
+ u32 mask;
|
|
|
+ int id, ret;
|
|
|
+
|
|
|
+ ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ WARN_ON(!i2c_dev->slave[id]);
|
|
|
+
|
|
|
+ if (id == 0) {
|
|
|
+ mask = STM32F7_I2C_OAR1_OA1EN;
|
|
|
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
|
|
|
+ } else {
|
|
|
+ mask = STM32F7_I2C_OAR2_OA2EN;
|
|
|
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
|
|
|
+ }
|
|
|
+
|
|
|
+ i2c_dev->slave[id] = NULL;
|
|
|
+
|
|
|
+ if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
|
|
|
+ stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
|
|
|
+ clk_disable(i2c_dev->clk);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
|
|
|
{
|
|
|
- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
|
+ return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
|
|
|
+ I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
|
|
+ I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
|
|
+ I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
|
|
|
+ I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC;
|
|
|
}
|
|
|
|
|
|
static struct i2c_algorithm stm32f7_i2c_algo = {
|
|
|
.master_xfer = stm32f7_i2c_xfer,
|
|
|
+ .smbus_xfer = stm32f7_i2c_smbus_xfer,
|
|
|
.functionality = stm32f7_i2c_func,
|
|
|
+ .reg_slave = stm32f7_i2c_reg_slave,
|
|
|
+ .unreg_slave = stm32f7_i2c_unreg_slave,
|
|
|
};
|
|
|
|
|
|
static int stm32f7_i2c_probe(struct platform_device *pdev)
|
|
|
@@ -815,6 +1789,7 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
|
|
|
u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
|
|
|
struct i2c_adapter *adap;
|
|
|
struct reset_control *rst;
|
|
|
+ dma_addr_t phy_addr;
|
|
|
int ret;
|
|
|
|
|
|
i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
|
|
|
@@ -825,6 +1800,7 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
|
|
|
i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
if (IS_ERR(i2c_dev->base))
|
|
|
return PTR_ERR(i2c_dev->base);
|
|
|
+ phy_addr = (dma_addr_t)res->start;
|
|
|
|
|
|
irq_event = irq_of_parse_and_map(np, 0);
|
|
|
if (!irq_event) {
|
|
|
@@ -871,8 +1847,11 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
|
|
|
|
|
|
i2c_dev->dev = &pdev->dev;
|
|
|
|
|
|
- ret = devm_request_irq(&pdev->dev, irq_event, stm32f7_i2c_isr_event, 0,
|
|
|
- pdev->name, i2c_dev);
|
|
|
+ ret = devm_request_threaded_irq(&pdev->dev, irq_event,
|
|
|
+ stm32f7_i2c_isr_event,
|
|
|
+ stm32f7_i2c_isr_event_thread,
|
|
|
+ IRQF_ONESHOT,
|
|
|
+ pdev->name, i2c_dev);
|
|
|
if (ret) {
|
|
|
dev_err(&pdev->dev, "Failed to request irq event %i\n",
|
|
|
irq_event);
|
|
|
@@ -924,6 +1903,11 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
|
|
|
|
|
|
init_completion(&i2c_dev->complete);
|
|
|
|
|
|
+ /* Init DMA config if supported */
|
|
|
+ i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
|
|
|
+ STM32F7_I2C_TXDR,
|
|
|
+ STM32F7_I2C_RXDR);
|
|
|
+
|
|
|
ret = i2c_add_adapter(adap);
|
|
|
if (ret)
|
|
|
goto clk_free;
|
|
|
@@ -946,6 +1930,11 @@ static int stm32f7_i2c_remove(struct platform_device *pdev)
|
|
|
{
|
|
|
struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
|
|
|
|
|
|
+ if (i2c_dev->dma) {
|
|
|
+ stm32_i2c_dma_free(i2c_dev->dma);
|
|
|
+ i2c_dev->dma = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
i2c_del_adapter(&i2c_dev->adap);
|
|
|
|
|
|
clk_unprepare(i2c_dev->clk);
|
Linus Torvalds