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@@ -1272,7 +1272,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
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if (!check_cmd(engine, desc, cmd, length, is_master,
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if (!check_cmd(engine, desc, cmd, length, is_master,
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&oacontrol_set)) {
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&oacontrol_set)) {
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- ret = -EINVAL;
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+ ret = -EACCES;
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break;
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break;
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}
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}
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@@ -1333,6 +1333,9 @@ int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
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* 5. GPGPU dispatch compute indirect registers.
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* 5. GPGPU dispatch compute indirect registers.
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* 6. TIMESTAMP register and Haswell CS GPR registers
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* 6. TIMESTAMP register and Haswell CS GPR registers
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* 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
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* 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
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+ * 8. Don't report cmd_check() failures as EINVAL errors to userspace;
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+ * rely on the HW to NOOP disallowed commands as it would without
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+ * the parser enabled.
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*/
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*/
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- return 7;
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+ return 8;
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}
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}
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