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@@ -55,6 +55,25 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
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upper_32_bits(value));
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}
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+static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
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+{
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+ gfxhub_v1_0_init_gart_pt_regs(adev);
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+
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+ WREG32(SOC15_REG_OFFSET(GC, 0,
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+ mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
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+ (u32)(adev->mc.gtt_start >> 12));
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+ WREG32(SOC15_REG_OFFSET(GC, 0,
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+ mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
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+ (u32)(adev->mc.gtt_start >> 44));
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+
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+ WREG32(SOC15_REG_OFFSET(GC, 0,
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+ mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
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+ (u32)(adev->mc.gtt_end >> 12));
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+ WREG32(SOC15_REG_OFFSET(GC, 0,
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+ mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
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+ (u32)(adev->mc.gtt_end >> 44));
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+}
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+
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int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
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{
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u32 tmp;
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@@ -62,9 +81,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
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u32 i;
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/* Program MC. */
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- gfxhub_v1_0_init_gart_pt_regs(adev);
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+ gfxhub_v1_0_init_gart_aperture_regs(adev);
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- /* Update configuration */
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
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adev->mc.vram_start >> 18);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
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@@ -165,21 +183,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
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0);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
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- /* setup context0 */
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- WREG32(SOC15_REG_OFFSET(GC, 0,
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- mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
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- (u32)(adev->mc.gtt_start >> 12));
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- WREG32(SOC15_REG_OFFSET(GC, 0,
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- mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
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- (u32)(adev->mc.gtt_start >> 44));
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-
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- WREG32(SOC15_REG_OFFSET(GC, 0,
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- mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
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- (u32)(adev->mc.gtt_end >> 12));
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- WREG32(SOC15_REG_OFFSET(GC, 0,
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- mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
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- (u32)(adev->mc.gtt_end >> 44));
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-
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WREG32(SOC15_REG_OFFSET(GC, 0,
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mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
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(u32)(adev->dummy_page.addr >> 12));
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