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@@ -394,6 +394,20 @@ static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
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return readl(regs);
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}
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+#define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \
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+ timeout_us) \
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+({ \
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+ void __iomem *regs = hisi_hba->regs + off; \
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+ readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \
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+})
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+
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+#define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \
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+ timeout_us) \
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+({ \
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+ void __iomem *regs = hisi_hba->regs + off; \
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+ readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
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+})
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+
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static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
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{
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struct pci_dev *pdev = hisi_hba->pci_dev;
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@@ -684,8 +698,8 @@ static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
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udelay(50);
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/* Ensure axi bus idle */
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- ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
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- 20000, 1000000);
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+ ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
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+ 20000, 1000000);
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if (ret) {
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dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
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return -EIO;
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@@ -1977,8 +1991,9 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
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hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
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/* wait until bus idle */
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- rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
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- AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
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+ rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
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+ AM_CURR_TRANS_RETURN, status,
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+ status == 0x3, 10, 100);
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if (rc) {
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dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
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return rc;
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@@ -2396,8 +2411,9 @@ static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
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AM_CTRL_GLOBAL, reg_val);
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/* wait until bus idle */
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- rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
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- AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
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+ rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
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+ AM_CURR_TRANS_RETURN, status,
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+ status == 0x3, 10, 100);
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if (rc) {
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dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
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clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
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