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@@ -1196,64 +1196,74 @@ static int ath10k_pci_hif_start(struct ath10k *ar)
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return 0;
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}
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-static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
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+static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
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{
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struct ath10k *ar;
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- struct ath10k_pci *ar_pci;
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- struct ath10k_ce_pipe *ce_hdl;
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- u32 buf_sz;
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- struct sk_buff *netbuf;
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- u32 ce_data;
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+ struct ath10k_ce_pipe *ce_pipe;
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+ struct ath10k_ce_ring *ce_ring;
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+ struct sk_buff *skb;
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+ int i;
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- buf_sz = pipe_info->buf_sz;
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+ ar = pci_pipe->hif_ce_state;
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+ ce_pipe = pci_pipe->ce_hdl;
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+ ce_ring = ce_pipe->dest_ring;
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- /* Unused Copy Engine */
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- if (buf_sz == 0)
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+ if (!ce_ring)
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return;
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- ar = pipe_info->hif_ce_state;
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- ar_pci = ath10k_pci_priv(ar);
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- ce_hdl = pipe_info->ce_hdl;
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+ if (!pci_pipe->buf_sz)
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+ return;
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- while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
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- &ce_data) == 0) {
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- dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
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- netbuf->len + skb_tailroom(netbuf),
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+ for (i = 0; i < ce_ring->nentries; i++) {
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+ skb = ce_ring->per_transfer_context[i];
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+ if (!skb)
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+ continue;
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+
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+ ce_ring->per_transfer_context[i] = NULL;
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+
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+ dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
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+ skb->len + skb_tailroom(skb),
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DMA_FROM_DEVICE);
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- dev_kfree_skb_any(netbuf);
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+ dev_kfree_skb_any(skb);
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}
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}
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-static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
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+static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
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{
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struct ath10k *ar;
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struct ath10k_pci *ar_pci;
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- struct ath10k_ce_pipe *ce_hdl;
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- struct sk_buff *netbuf;
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- u32 ce_data;
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- unsigned int nbytes;
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+ struct ath10k_ce_pipe *ce_pipe;
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+ struct ath10k_ce_ring *ce_ring;
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+ struct ce_desc *ce_desc;
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+ struct sk_buff *skb;
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unsigned int id;
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- u32 buf_sz;
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+ int i;
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- buf_sz = pipe_info->buf_sz;
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+ ar = pci_pipe->hif_ce_state;
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+ ar_pci = ath10k_pci_priv(ar);
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+ ce_pipe = pci_pipe->ce_hdl;
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+ ce_ring = ce_pipe->src_ring;
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- /* Unused Copy Engine */
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- if (buf_sz == 0)
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+ if (!ce_ring)
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return;
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- ar = pipe_info->hif_ce_state;
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- ar_pci = ath10k_pci_priv(ar);
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- ce_hdl = pipe_info->ce_hdl;
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+ if (!pci_pipe->buf_sz)
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+ return;
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- while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
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- &ce_data, &nbytes, &id) == 0) {
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- /* no need to call tx completion for NULL pointers */
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- if (!netbuf)
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+ ce_desc = ce_ring->shadow_base;
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+ if (WARN_ON(!ce_desc))
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+ return;
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+
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+ for (i = 0; i < ce_ring->nentries; i++) {
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+ skb = ce_ring->per_transfer_context[i];
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+ if (!skb)
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continue;
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- ar_pci->msg_callbacks_current.tx_completion(ar,
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- netbuf,
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- id);
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+ ce_ring->per_transfer_context[i] = NULL;
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+ id = MS(__le16_to_cpu(ce_desc[i].flags),
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+ CE_DESC_FLAGS_META_DATA);
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+
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+ ar_pci->msg_callbacks_current.tx_completion(ar, skb, id);
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}
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}
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@@ -1432,6 +1442,9 @@ static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
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&nbytes, &transfer_id, &flags))
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return;
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+ if (WARN_ON_ONCE(!xfer))
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+ return;
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+
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if (!xfer->wait_for_resp) {
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ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
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return;
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@@ -1707,99 +1720,167 @@ static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
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msleep(10);
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}
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-static int ath10k_pci_warm_reset(struct ath10k *ar)
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+static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
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{
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u32 val;
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- ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
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-
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- spin_lock_bh(&ar->data_lock);
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-
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- ar->stats.fw_warm_reset_counter++;
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-
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- spin_unlock_bh(&ar->data_lock);
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-
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- /* debug */
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- val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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- PCIE_INTR_CAUSE_ADDRESS);
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- ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n",
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- val);
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+ ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
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- val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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- CPU_INTR_ADDRESS);
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- ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
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- val);
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+ val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
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+ SOC_RESET_CONTROL_ADDRESS);
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+ ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
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+ val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
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+}
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- /* disable pending irqs */
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- ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
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- PCIE_INTR_ENABLE_ADDRESS, 0);
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+static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
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+{
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+ u32 val;
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- ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
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- PCIE_INTR_CLR_ADDRESS, ~0);
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+ val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
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+ SOC_RESET_CONTROL_ADDRESS);
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- msleep(100);
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+ ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
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+ val | SOC_RESET_CONTROL_CE_RST_MASK);
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+ msleep(10);
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+ ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
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+ val & ~SOC_RESET_CONTROL_CE_RST_MASK);
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+}
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- /* clear fw indicator */
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- ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
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+static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
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+{
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+ u32 val;
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- /* clear target LF timer interrupts */
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val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
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SOC_LF_TIMER_CONTROL0_ADDRESS);
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ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
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SOC_LF_TIMER_CONTROL0_ADDRESS,
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val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
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+}
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- /* reset CE */
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- val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
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- SOC_RESET_CONTROL_ADDRESS);
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- ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
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- val | SOC_RESET_CONTROL_CE_RST_MASK);
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- val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
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- SOC_RESET_CONTROL_ADDRESS);
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- msleep(10);
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+static int ath10k_pci_warm_reset(struct ath10k *ar)
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+{
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+ int ret;
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- /* unreset CE */
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- ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
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- val & ~SOC_RESET_CONTROL_CE_RST_MASK);
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- val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
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- SOC_RESET_CONTROL_ADDRESS);
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- msleep(10);
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+ ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
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+
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+ spin_lock_bh(&ar->data_lock);
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+ ar->stats.fw_warm_reset_counter++;
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+ spin_unlock_bh(&ar->data_lock);
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+ ath10k_pci_irq_disable(ar);
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+
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+ /* Make sure the target CPU is not doing anything dangerous, e.g. if it
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+ * were to access copy engine while host performs copy engine reset
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+ * then it is possible for the device to confuse pci-e controller to
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+ * the point of bringing host system to a complete stop (i.e. hang).
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+ */
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ath10k_pci_warm_reset_si0(ar);
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+ ath10k_pci_warm_reset_cpu(ar);
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+ ath10k_pci_init_pipes(ar);
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+ ath10k_pci_wait_for_target_init(ar);
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- /* debug */
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- val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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- PCIE_INTR_CAUSE_ADDRESS);
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- ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n",
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- val);
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+ ath10k_pci_warm_reset_clear_lf(ar);
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+ ath10k_pci_warm_reset_ce(ar);
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+ ath10k_pci_warm_reset_cpu(ar);
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+ ath10k_pci_init_pipes(ar);
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- val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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- CPU_INTR_ADDRESS);
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- ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
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- val);
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+ ret = ath10k_pci_wait_for_target_init(ar);
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+ if (ret) {
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+ ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
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+ return ret;
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+ }
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- /* CPU warm reset */
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- val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
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- SOC_RESET_CONTROL_ADDRESS);
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- ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
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- val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
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+ ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
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- val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
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- SOC_RESET_CONTROL_ADDRESS);
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- ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n",
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- val);
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+ return 0;
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+}
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- msleep(100);
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+static int ath10k_pci_chip_reset(struct ath10k *ar)
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+{
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+ int i, ret;
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+ u32 val;
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- ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
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+ ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset\n");
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+
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+ /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
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+ * It is thus preferred to use warm reset which is safer but may not be
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+ * able to recover the device from all possible fail scenarios.
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+ *
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+ * Warm reset doesn't always work on first try so attempt it a few
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+ * times before giving up.
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+ */
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+ for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
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+ ret = ath10k_pci_warm_reset(ar);
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+ if (ret) {
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+ ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
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+ i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
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+ ret);
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+ continue;
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+ }
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+
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+ /* FIXME: Sometimes copy engine doesn't recover after warm
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+ * reset. In most cases this needs cold reset. In some of these
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+ * cases the device is in such a state that a cold reset may
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+ * lock up the host.
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+ *
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+ * Reading any host interest register via copy engine is
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+ * sufficient to verify if device is capable of booting
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+ * firmware blob.
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+ */
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+ ret = ath10k_pci_init_pipes(ar);
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+ if (ret) {
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+ ath10k_warn(ar, "failed to init copy engine: %d\n",
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+ ret);
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+ continue;
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+ }
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+
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+ ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
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+ &val);
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+ if (ret) {
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+ ath10k_warn(ar, "failed to poke copy engine: %d\n",
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+ ret);
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+ continue;
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+ }
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+
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+ ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
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+ return 0;
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+ }
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+
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+ if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
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+ ath10k_warn(ar, "refusing cold reset as requested\n");
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+ return -EPERM;
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+ }
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+
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+ ret = ath10k_pci_cold_reset(ar);
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+ if (ret) {
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+ ath10k_warn(ar, "failed to cold reset: %d\n", ret);
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+ return ret;
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+ }
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+
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+ ret = ath10k_pci_wait_for_target_init(ar);
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+ if (ret) {
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+ ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
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+ ret);
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+ return ret;
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+ }
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+
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+ ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (cold)\n");
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return 0;
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}
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-static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
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+static int ath10k_pci_hif_power_up(struct ath10k *ar)
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{
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int ret;
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+ ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
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+
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+ ret = ath10k_pci_wake(ar);
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+ if (ret) {
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+ ath10k_err(ar, "failed to wake up target: %d\n", ret);
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+ return ret;
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+ }
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+
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/*
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* Bring the target up cleanly.
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*
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@@ -1810,26 +1891,16 @@ static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
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* is in an unexpected state. We try to catch that here in order to
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* reset the Target and retry the probe.
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*/
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- if (cold_reset)
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- ret = ath10k_pci_cold_reset(ar);
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- else
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- ret = ath10k_pci_warm_reset(ar);
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-
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+ ret = ath10k_pci_chip_reset(ar);
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if (ret) {
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- ath10k_err(ar, "failed to reset target: %d\n", ret);
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- goto err;
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+ ath10k_err(ar, "failed to reset chip: %d\n", ret);
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+ goto err_sleep;
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}
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ret = ath10k_pci_init_pipes(ar);
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if (ret) {
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ath10k_err(ar, "failed to initialize CE: %d\n", ret);
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- goto err;
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- }
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-
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- ret = ath10k_pci_wait_for_target_init(ar);
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- if (ret) {
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- ath10k_err(ar, "failed to wait for target to init: %d\n", ret);
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- goto err_ce;
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+ goto err_sleep;
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}
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ret = ath10k_pci_init_config(ar);
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@@ -1848,73 +1919,21 @@ static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
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err_ce:
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ath10k_pci_ce_deinit(ar);
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- ath10k_pci_warm_reset(ar);
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-err:
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- return ret;
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-}
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-
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-static int ath10k_pci_hif_power_up_warm(struct ath10k *ar)
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-{
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- int i, ret;
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-
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- /*
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- * Sometime warm reset succeeds after retries.
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- *
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- * FIXME: It might be possible to tune ath10k_pci_warm_reset() to work
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- * at first try.
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- */
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- for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
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- ret = __ath10k_pci_hif_power_up(ar, false);
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- if (ret == 0)
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- break;
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-
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- ath10k_warn(ar, "failed to warm reset (attempt %d out of %d): %d\n",
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- i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, ret);
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- }
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+err_sleep:
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+ ath10k_pci_sleep(ar);
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return ret;
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}
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-static int ath10k_pci_hif_power_up(struct ath10k *ar)
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-{
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- int ret;
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-
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- ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
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-
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- /*
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- * Hardware CUS232 version 2 has some issues with cold reset and the
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- * preferred (and safer) way to perform a device reset is through a
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- * warm reset.
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- *
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- * Warm reset doesn't always work though so fall back to cold reset may
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- * be necessary.
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- */
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- ret = ath10k_pci_hif_power_up_warm(ar);
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- if (ret) {
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- ath10k_warn(ar, "failed to power up target using warm reset: %d\n",
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- ret);
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-
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- if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY)
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- return ret;
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-
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- ath10k_warn(ar, "trying cold reset\n");
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-
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- ret = __ath10k_pci_hif_power_up(ar, true);
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- if (ret) {
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- ath10k_err(ar, "failed to power up target using cold reset too (%d)\n",
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- ret);
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- return ret;
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- }
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- }
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-
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- return 0;
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-}
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-
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static void ath10k_pci_hif_power_down(struct ath10k *ar)
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{
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ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
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- ath10k_pci_warm_reset(ar);
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+ /* Currently hif_power_up performs effectively a reset and hif_stop
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+ * resets the chip as well so there's no point in resetting here.
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+ */
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+
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+ ath10k_pci_sleep(ar);
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}
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#ifdef CONFIG_PM
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@@ -2516,6 +2535,8 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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goto err_deinit_irq;
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}
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+ ath10k_pci_sleep(ar);
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+
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ret = ath10k_core_register(ar, chip_id);
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if (ret) {
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ath10k_err(ar, "failed to register driver core: %d\n", ret);
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@@ -2567,7 +2588,6 @@ static void ath10k_pci_remove(struct pci_dev *pdev)
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ath10k_pci_deinit_irq(ar);
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ath10k_pci_ce_deinit(ar);
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ath10k_pci_free_pipes(ar);
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- ath10k_pci_sleep(ar);
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ath10k_pci_release(ar);
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ath10k_core_destroy(ar);
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}
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John W. Linville