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@@ -302,13 +302,15 @@ void init_comet(void *ci, struct s_comet_reg *comet, u_int32_t port_mode, int cl
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pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
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if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
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if (cxt1e1_log_level >= LOG_SBEBUG12)
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- pr_info(">> %s: clockmaster internal clock\n", __func__);
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+ pr_info(">> %s: clockmaster internal clock\n",
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+ __func__);
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/* internal oscillator */
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pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
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} else {
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/* external clock source */
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if (cxt1e1_log_level >= LOG_SBEBUG12)
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- pr_info(">> %s: clockmaster external clock\n", __func__);
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+ pr_info(">> %s: clockmaster external clock\n",
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+ __func__);
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/* loop timing(external) */
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pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
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}
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@@ -421,11 +423,13 @@ WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
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for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
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for (unit = 0; unit < COMET_NUM_UNITS; unit++)
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- WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
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+ WrtXmtWaveform(ci, comet, sample, unit,
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+ table[sample][unit]);
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}
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/* Enable transmitter and set output amplitude */
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- pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
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+ pci_write_32((u_int32_t *) &comet->xlpg_cfg,
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+ table[COMET_NUM_SAMPLES][0]);
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}
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@@ -453,7 +457,8 @@ WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
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/* for write order preservation when Optimizing driver */
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pci_flush_write(ci);
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/* write the addr, initiate a read */
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- pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
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+ pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
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+ (u_int8_t) ramaddr);
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/* for write order preservation when Optimizing driver */
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pci_flush_write(ci);
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/*
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@@ -466,9 +471,12 @@ WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
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}
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value = *table++;
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- pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
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- pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
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- pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
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+ pci_write_32((u_int32_t *) &comet->rlps_idata3,
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+ (u_int8_t) (value >> 24));
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+ pci_write_32((u_int32_t *) &comet->rlps_idata2,
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+ (u_int8_t) (value >> 16));
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+ pci_write_32((u_int32_t *) &comet->rlps_idata1,
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+ (u_int8_t) (value >> 8));
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pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
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/* for write order preservation when Optimizing driver */
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pci_flush_write(ci);
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@@ -480,7 +488,8 @@ WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
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/* for write order preservation when optimizing driver */
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pci_flush_write(ci);
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/* write the addr, initiate a read */
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- pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
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+ pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
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+ (u_int8_t) ramaddr);
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/* for write order preservation when optimizing driver */
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pci_flush_write(ci);
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