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@@ -48,6 +48,8 @@
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#define WRITEL(data, reg) \
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(WARN_ON_ONCE(!(reg)) ? 0 : writel((data), (reg)))
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+#define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
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+
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/* Allocate temporary buffers for decoding */
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static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
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{
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@@ -1352,7 +1354,7 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
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WRITEL(ctx->display_delay, mfc_regs->d_display_delay);
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}
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- if (IS_MFCV7_PLUS(dev)) {
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+ if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) {
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WRITEL(reg, mfc_regs->d_dec_options);
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reg = 0;
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}
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@@ -1367,7 +1369,7 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
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if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
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reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
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- if (IS_MFCV7_PLUS(dev))
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+ if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev))
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WRITEL(reg, mfc_regs->d_init_buffer_options);
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else
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WRITEL(reg, mfc_regs->d_dec_options);
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