|
@@ -516,8 +516,6 @@ static int wil_target_reset(struct wil6210_priv *wil)
|
|
|
{
|
|
|
int delay = 0;
|
|
|
u32 x;
|
|
|
- bool is_reset_v2 = test_bit(hw_capability_reset_v2,
|
|
|
- wil->hw_capabilities);
|
|
|
|
|
|
wil_dbg_misc(wil, "Resetting \"%s\"...\n", wil->hw_name);
|
|
|
|
|
@@ -533,52 +531,39 @@ static int wil_target_reset(struct wil6210_priv *wil)
|
|
|
/* Clear Fw Download notification */
|
|
|
C(RGF_USER_USAGE_6, BIT(0));
|
|
|
|
|
|
- if (is_reset_v2) {
|
|
|
- S(RGF_CAF_OSC_CONTROL, BIT_CAF_OSC_XTAL_EN);
|
|
|
- /* XTAL stabilization should take about 3ms */
|
|
|
- usleep_range(5000, 7000);
|
|
|
- x = R(RGF_CAF_PLL_LOCK_STATUS);
|
|
|
- if (!(x & BIT_CAF_OSC_DIG_XTAL_STABLE)) {
|
|
|
- wil_err(wil, "Xtal stabilization timeout\n"
|
|
|
- "RGF_CAF_PLL_LOCK_STATUS = 0x%08x\n", x);
|
|
|
- return -ETIME;
|
|
|
- }
|
|
|
- /* switch 10k to XTAL*/
|
|
|
- C(RGF_USER_SPARROW_M_4, BIT_SPARROW_M_4_SEL_SLEEP_OR_REF);
|
|
|
- /* 40 MHz */
|
|
|
- C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_CAR_AHB_SW_SEL);
|
|
|
-
|
|
|
- W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f);
|
|
|
- W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0xf);
|
|
|
+ S(RGF_CAF_OSC_CONTROL, BIT_CAF_OSC_XTAL_EN);
|
|
|
+ /* XTAL stabilization should take about 3ms */
|
|
|
+ usleep_range(5000, 7000);
|
|
|
+ x = R(RGF_CAF_PLL_LOCK_STATUS);
|
|
|
+ if (!(x & BIT_CAF_OSC_DIG_XTAL_STABLE)) {
|
|
|
+ wil_err(wil, "Xtal stabilization timeout\n"
|
|
|
+ "RGF_CAF_PLL_LOCK_STATUS = 0x%08x\n", x);
|
|
|
+ return -ETIME;
|
|
|
}
|
|
|
+ /* switch 10k to XTAL*/
|
|
|
+ C(RGF_USER_SPARROW_M_4, BIT_SPARROW_M_4_SEL_SLEEP_OR_REF);
|
|
|
+ /* 40 MHz */
|
|
|
+ C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_CAR_AHB_SW_SEL);
|
|
|
+
|
|
|
+ W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f);
|
|
|
+ W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0xf);
|
|
|
|
|
|
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);
|
|
|
W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F);
|
|
|
- W(RGF_USER_CLKS_CTL_SW_RST_VEC_3,
|
|
|
- is_reset_v2 ? 0x000000f0 : 0x00000170);
|
|
|
+ W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x000000f0);
|
|
|
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FE00);
|
|
|
|
|
|
- if (is_reset_v2) {
|
|
|
- W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0);
|
|
|
- W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0x0);
|
|
|
- }
|
|
|
+ W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0);
|
|
|
+ W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0x0);
|
|
|
|
|
|
W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
|
|
|
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
|
|
|
W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
|
|
|
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
|
|
|
|
|
|
- if (is_reset_v2) {
|
|
|
- W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003);
|
|
|
- /* reset A2 PCIE AHB */
|
|
|
- W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
|
|
|
- } else {
|
|
|
- W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000001);
|
|
|
- W(RGF_PCIE_LOS_COUNTER_CTL, BIT(6) | BIT(8));
|
|
|
- W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
|
|
|
- }
|
|
|
+ W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003);
|
|
|
+ W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000); /* reset A2 PCIE AHB */
|
|
|
|
|
|
- /* TODO: check order here!!! Erez code is different */
|
|
|
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
|
|
|
|
|
|
/* wait until device ready. typical time is 20..80 msec */
|
|
@@ -592,9 +577,6 @@ static int wil_target_reset(struct wil6210_priv *wil)
|
|
|
}
|
|
|
} while (!(x & BIT_BL_READY));
|
|
|
|
|
|
- if (!is_reset_v2)
|
|
|
- W(RGF_PCIE_LOS_COUNTER_CTL, BIT(8));
|
|
|
-
|
|
|
C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
|
|
|
|
|
|
wil_dbg_misc(wil, "Reset completed in %d ms\n", delay * RST_DELAY);
|