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@@ -45,6 +45,10 @@
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/* LPC bus IO offsets */
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#define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000
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#define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500
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+#define MLXPLAT_CPLD_LPC_REG_AGGR_ADRR 0x253a
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+#define MLXPLAT_CPLD_LPC_REG_PSU_ADRR 0x2558
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+#define MLXPLAT_CPLD_LPC_REG_PWR_ADRR 0x2564
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+#define MLXPLAT_CPLD_LPC_REG_FAN_ADRR 0x2588
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#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
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#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
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#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
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@@ -56,6 +60,17 @@
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MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \
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MLXPLAT_CPLD_LPC_PIO_OFFSET)
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+/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */
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+#define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08
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+#define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08
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+#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40
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+#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
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+ MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
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+#define MLXPLAT_CPLD_AGGR_MASK_MSN21XX 0x04
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+#define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
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+#define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
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+#define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0)
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+
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/* Start channel numbers */
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#define MLXPLAT_CPLD_CH1 2
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#define MLXPLAT_CPLD_CH2 10
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@@ -123,7 +138,7 @@ static struct i2c_mux_reg_platform_data mlxplat_mux_data[] = {
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};
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/* Platform hotplug devices */
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-static struct mlxcpld_hotplug_device mlxplat_mlxcpld_hotplug_psu[] = {
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+static struct mlxcpld_hotplug_device mlxplat_mlxcpld_psu[] = {
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{
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.brdinfo = { I2C_BOARD_INFO("24c02", 0x51) },
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.bus = 10,
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@@ -134,7 +149,7 @@ static struct mlxcpld_hotplug_device mlxplat_mlxcpld_hotplug_psu[] = {
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},
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};
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-static struct mlxcpld_hotplug_device mlxplat_mlxcpld_hotplug_pwr[] = {
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+static struct mlxcpld_hotplug_device mlxplat_mlxcpld_pwr[] = {
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{
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.brdinfo = { I2C_BOARD_INFO("dps460", 0x59) },
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.bus = 10,
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@@ -145,7 +160,7 @@ static struct mlxcpld_hotplug_device mlxplat_mlxcpld_hotplug_pwr[] = {
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},
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};
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-static struct mlxcpld_hotplug_device mlxplat_mlxcpld_hotplug_fan[] = {
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+static struct mlxcpld_hotplug_device mlxplat_mlxcpld_fan[] = {
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{
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.brdinfo = { I2C_BOARD_INFO("24c32", 0x50) },
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.bus = 11,
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@@ -166,38 +181,38 @@ static struct mlxcpld_hotplug_device mlxplat_mlxcpld_hotplug_fan[] = {
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/* Platform hotplug default data */
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static
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-struct mlxcpld_hotplug_platform_data mlxplat_mlxcpld_hotplug_default_data = {
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- .top_aggr_offset = (MLXPLAT_CPLD_LPC_REG_BASE_ADRR | 0x3a),
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- .top_aggr_mask = 0x48,
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- .top_aggr_psu_mask = 0x08,
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- .psu_reg_offset = (MLXPLAT_CPLD_LPC_REG_BASE_ADRR | 0x58),
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- .psu_mask = 0x03,
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- .psu_count = ARRAY_SIZE(mlxplat_mlxcpld_hotplug_psu),
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- .psu = mlxplat_mlxcpld_hotplug_psu,
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- .top_aggr_pwr_mask = 0x08,
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- .pwr_reg_offset = (MLXPLAT_CPLD_LPC_REG_BASE_ADRR | 0x64),
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- .pwr_mask = 0x03,
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- .pwr_count = ARRAY_SIZE(mlxplat_mlxcpld_hotplug_pwr),
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- .pwr = mlxplat_mlxcpld_hotplug_pwr,
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- .top_aggr_fan_mask = 0x40,
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- .fan_reg_offset = (MLXPLAT_CPLD_LPC_REG_BASE_ADRR | 0x88),
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- .fan_mask = 0x0f,
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- .fan_count = ARRAY_SIZE(mlxplat_mlxcpld_hotplug_fan),
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- .fan = mlxplat_mlxcpld_hotplug_fan,
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+struct mlxcpld_hotplug_platform_data mlxplat_mlxcpld_default_data = {
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+ .top_aggr_offset = MLXPLAT_CPLD_LPC_REG_AGGR_ADRR,
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+ .top_aggr_mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
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+ .top_aggr_psu_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF,
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+ .psu_reg_offset = MLXPLAT_CPLD_LPC_REG_PSU_ADRR,
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+ .psu_mask = MLXPLAT_CPLD_PSU_MASK,
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+ .psu_count = ARRAY_SIZE(mlxplat_mlxcpld_psu),
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+ .psu = mlxplat_mlxcpld_psu,
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+ .top_aggr_pwr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
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+ .pwr_reg_offset = MLXPLAT_CPLD_LPC_REG_PWR_ADRR,
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+ .pwr_mask = MLXPLAT_CPLD_PWR_MASK,
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+ .pwr_count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
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+ .pwr = mlxplat_mlxcpld_pwr,
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+ .top_aggr_fan_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF,
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+ .fan_reg_offset = MLXPLAT_CPLD_LPC_REG_FAN_ADRR,
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+ .fan_mask = MLXPLAT_CPLD_FAN_MASK,
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+ .fan_count = ARRAY_SIZE(mlxplat_mlxcpld_fan),
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+ .fan = mlxplat_mlxcpld_fan,
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};
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/* Platform hotplug MSN21xx system family data */
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static
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-struct mlxcpld_hotplug_platform_data mlxplat_mlxcpld_hotplug_msn21xx_data = {
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- .top_aggr_offset = (MLXPLAT_CPLD_LPC_REG_BASE_ADRR | 0x3a),
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- .top_aggr_mask = 0x04,
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- .top_aggr_pwr_mask = 0x04,
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- .pwr_reg_offset = (MLXPLAT_CPLD_LPC_REG_BASE_ADRR | 0x64),
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- .pwr_mask = 0x03,
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- .pwr_count = ARRAY_SIZE(mlxplat_mlxcpld_hotplug_pwr),
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+struct mlxcpld_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {
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+ .top_aggr_offset = MLXPLAT_CPLD_LPC_REG_AGGR_ADRR,
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+ .top_aggr_mask = MLXPLAT_CPLD_AGGR_MASK_MSN21XX,
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+ .top_aggr_pwr_mask = MLXPLAT_CPLD_AGGR_MASK_MSN21XX,
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+ .pwr_reg_offset = MLXPLAT_CPLD_LPC_REG_PWR_ADRR,
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+ .pwr_mask = MLXPLAT_CPLD_PWR_MASK,
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+ .pwr_count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
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};
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-static struct resource mlxplat_mlxcpld_hotplug_resources[] = {
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+static struct resource mlxplat_mlxcpld_resources[] = {
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[0] = DEFINE_RES_IRQ_NAMED(17, "mlxcpld-hotplug"),
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};
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@@ -213,7 +228,7 @@ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)
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mlxplat_mux_data[i].n_values =
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ARRAY_SIZE(mlxplat_default_channels[i]);
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}
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- mlxplat_hotplug = &mlxplat_mlxcpld_hotplug_default_data;
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+ mlxplat_hotplug = &mlxplat_mlxcpld_default_data;
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return 1;
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};
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@@ -227,7 +242,7 @@ static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
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mlxplat_mux_data[i].n_values =
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ARRAY_SIZE(mlxplat_msn21xx_channels);
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}
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- mlxplat_hotplug = &mlxplat_mlxcpld_hotplug_msn21xx_data;
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+ mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data;
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return 1;
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};
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@@ -314,9 +329,10 @@ static int __init mlxplat_init(void)
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}
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priv->pdev_hotplug = platform_device_register_resndata(
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- &mlxplat_dev->dev, "mlxcpld-hotplug", -1,
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- mlxplat_mlxcpld_hotplug_resources,
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- ARRAY_SIZE(mlxplat_mlxcpld_hotplug_resources),
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+ &mlxplat_dev->dev, "mlxcpld-hotplug",
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+ PLATFORM_DEVID_NONE,
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+ mlxplat_mlxcpld_resources,
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+ ARRAY_SIZE(mlxplat_mlxcpld_resources),
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mlxplat_hotplug, sizeof(*mlxplat_hotplug));
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if (IS_ERR(priv->pdev_hotplug)) {
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err = PTR_ERR(priv->pdev_hotplug);
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