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@@ -1,7 +1,7 @@
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/*
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* DMA driver for Nvidia's Tegra20 APB DMA controller.
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*
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- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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+ * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -29,6 +29,7 @@
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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+#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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@@ -199,6 +200,7 @@ struct tegra_dma_channel {
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void *callback_param;
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/* Channel-slave specific configuration */
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+ unsigned int slave_id;
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struct dma_slave_config dma_sconfig;
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struct tegra_dma_channel_regs channel_reg;
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};
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@@ -340,6 +342,8 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
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}
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memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
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+ if (!tdc->slave_id)
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+ tdc->slave_id = sconfig->slave_id;
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tdc->config_init = true;
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return 0;
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}
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@@ -942,7 +946,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
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ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
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csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
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- csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
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+ csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
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if (flags & DMA_PREP_INTERRUPT)
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csr |= TEGRA_APBDMA_CSR_IE_EOC;
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@@ -1086,7 +1090,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
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csr |= TEGRA_APBDMA_CSR_FLOW;
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if (flags & DMA_PREP_INTERRUPT)
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csr |= TEGRA_APBDMA_CSR_IE_EOC;
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- csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
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+ csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
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apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
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@@ -1206,6 +1210,25 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
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kfree(sg_req);
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}
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clk_disable_unprepare(tdma->dma_clk);
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+
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+ tdc->slave_id = 0;
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+}
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+
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+static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
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+ struct of_dma *ofdma)
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+{
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+ struct tegra_dma *tdma = ofdma->of_dma_data;
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+ struct dma_chan *chan;
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+ struct tegra_dma_channel *tdc;
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+
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+ chan = dma_get_any_slave_channel(&tdma->dma_dev);
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+ if (!chan)
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+ return NULL;
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+
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+ tdc = to_tegra_dma_chan(chan);
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+ tdc->slave_id = dma_spec->args[0];
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+
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+ return chan;
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}
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/* Tegra20 specific DMA controller information */
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@@ -1383,10 +1406,20 @@ static int tegra_dma_probe(struct platform_device *pdev)
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goto err_irq;
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}
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+ ret = of_dma_controller_register(pdev->dev.of_node,
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+ tegra_dma_of_xlate, tdma);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev,
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+ "Tegra20 APB DMA OF registration failed %d\n", ret);
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+ goto err_unregister_dma_dev;
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+ }
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+
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dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
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cdata->nr_channels);
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return 0;
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+err_unregister_dma_dev:
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+ dma_async_device_unregister(&tdma->dma_dev);
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err_irq:
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while (--i >= 0) {
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struct tegra_dma_channel *tdc = &tdma->channels[i];
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