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@@ -45,4 +45,8 @@
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#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
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#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
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#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
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#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
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+//DF_CS_AON0_CoherentSlaveModeCtrlA0
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+#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT 0x3
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+#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK 0x00000008L
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+
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#endif
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#endif
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