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@@ -1871,13 +1871,6 @@ static struct cntr_entry port_cntrs[PORT_CNTR_LAST] = {
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/* ======================================================================== */
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-/* return true if this is chip revision revision a0 */
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-int is_a0(struct hfi1_devdata *dd)
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-{
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- return ((dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
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- & CCE_REVISION_CHIP_REV_MINOR_MASK) == 0;
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-}
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-
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/* return true if this is chip revision revision a */
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int is_ax(struct hfi1_devdata *dd)
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{
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@@ -1893,7 +1886,7 @@ int is_bx(struct hfi1_devdata *dd)
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u8 chip_rev_minor =
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dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT
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& CCE_REVISION_CHIP_REV_MINOR_MASK;
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- return !!(chip_rev_minor & 0x10);
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+ return (chip_rev_minor & 0xF0) == 0x10;
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}
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/*
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@@ -2188,9 +2181,8 @@ static void handle_cce_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
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dd_dev_info(dd, "CCE Error: %s\n",
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cce_err_status_string(buf, sizeof(buf), reg));
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- if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK)
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- && is_a0(dd)
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- && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
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+ if ((reg & CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK) &&
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+ is_ax(dd) && (dd->icode != ICODE_FUNCTIONAL_SIMULATOR)) {
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/* this error requires a manual drop into SPC freeze mode */
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/* then a fix up */
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start_freeze_handling(dd->pport, FREEZE_SELF);
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@@ -2250,7 +2242,7 @@ static void handle_rxe_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
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* Freeze mode recovery is disabled for the errors
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* in RXE_FREEZE_ABORT_MASK
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*/
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- if (is_a0(dd) && (reg & RXE_FREEZE_ABORT_MASK))
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+ if (is_ax(dd) && (reg & RXE_FREEZE_ABORT_MASK))
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flags = FREEZE_ABORT;
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start_freeze_handling(dd->pport, flags);
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@@ -2353,7 +2345,7 @@ static void handle_egress_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
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if (reg & ALL_TXE_EGRESS_FREEZE_ERR)
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start_freeze_handling(dd->pport, 0);
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- if (is_a0(dd) && (reg &
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+ if (is_ax(dd) && (reg &
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SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK)
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&& (dd->icode != ICODE_FUNCTIONAL_SIMULATOR))
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start_freeze_handling(dd->pport, 0);
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@@ -3048,7 +3040,7 @@ static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata *dd)
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/* else this is _p */
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version = emulator_rev(dd);
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- if (!is_a0(dd))
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+ if (!is_ax(dd))
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version = 0x2d; /* all B0 use 0x2d or higher settings */
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if (version <= 0x12) {
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@@ -3334,7 +3326,7 @@ void handle_freeze(struct work_struct *work)
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write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
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wait_for_freeze_status(dd, 0);
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- if (is_a0(dd)) {
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+ if (is_ax(dd)) {
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write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_FREEZE_SMASK);
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wait_for_freeze_status(dd, 1);
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write_csr(dd, CCE_CTRL, CCE_CTRL_SPC_UNFREEZE_SMASK);
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@@ -3862,7 +3854,7 @@ void handle_verify_cap(struct work_struct *work)
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* REPLAY_BUF_MBE_SMASK
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* FLIT_INPUT_BUF_MBE_SMASK
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*/
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- if (is_a0(dd)) { /* fixed in B0 */
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+ if (is_ax(dd)) { /* fixed in B0 */
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reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
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reg |= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
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| DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK;
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@@ -7329,8 +7321,8 @@ static int set_buffer_control(struct hfi1_devdata *dd,
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*/
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use_all_mask = 0;
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if ((be16_to_cpu(new_bc->overall_shared_limit) <
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- be16_to_cpu(cur_bc.overall_shared_limit))
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- || (is_a0(dd) && any_shared_limit_changing)) {
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+ be16_to_cpu(cur_bc.overall_shared_limit)) ||
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+ (is_ax(dd) && any_shared_limit_changing)) {
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set_global_shared(dd, 0);
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cur_bc.overall_shared_limit = 0;
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use_all_mask = 1;
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@@ -7504,7 +7496,7 @@ int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t)
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*/
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static int disable_data_vls(struct hfi1_devdata *dd)
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{
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- if (is_a0(dd))
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+ if (is_ax(dd))
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return 1;
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pio_send_control(dd, PSC_DATA_VL_DISABLE);
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@@ -7522,7 +7514,7 @@ static int disable_data_vls(struct hfi1_devdata *dd)
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*/
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int open_fill_data_vls(struct hfi1_devdata *dd)
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{
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- if (is_a0(dd))
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+ if (is_ax(dd))
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return 1;
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pio_send_control(dd, PSC_DATA_VL_ENABLE);
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@@ -9972,7 +9964,7 @@ static void init_chip(struct hfi1_devdata *dd)
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/* restore command and BARs */
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restore_pci_variables(dd);
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- if (is_a0(dd)) {
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+ if (is_ax(dd)) {
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dd_dev_info(dd, "Resetting CSRs with FLR\n");
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hfi1_pcie_flr(dd);
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restore_pci_variables(dd);
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@@ -9991,7 +9983,7 @@ static void init_chip(struct hfi1_devdata *dd)
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write_csr(dd, CCE_DC_CTRL, 0);
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/* Set the LED off */
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- if (is_a0(dd))
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+ if (is_ax(dd))
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setextled(dd, 0);
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/*
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* Clear the QSFP reset.
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@@ -10014,7 +10006,7 @@ static void init_early_variables(struct hfi1_devdata *dd)
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/* assign link credit variables */
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dd->vau = CM_VAU;
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dd->link_credits = CM_GLOBAL_CREDITS;
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- if (is_a0(dd))
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+ if (is_ax(dd))
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dd->link_credits--;
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dd->vcu = cu_to_vcu(hfi1_cu);
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/* enough room for 8 MAD packets plus header - 17K */
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@@ -10122,7 +10114,7 @@ static void init_qos(struct hfi1_devdata *dd, u32 first_ctxt)
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unsigned qpns_per_vl, ctxt, i, qpn, n = 1, m;
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u64 *rsmmap;
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u64 reg;
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- u8 rxcontext = is_a0(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */
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+ u8 rxcontext = is_ax(dd) ? 0 : 0xff; /* 0 is default if a0 ver. */
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/* validate */
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if (dd->n_krcv_queues <= MIN_KERNEL_KCTXTS ||
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@@ -10327,7 +10319,7 @@ int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey)
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* Enable send-side J_KEY integrity check, unless this is A0 h/w
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* (due to A0 erratum).
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*/
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- if (!is_a0(dd)) {
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+ if (!is_ax(dd)) {
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reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
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reg |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
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write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
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@@ -10360,7 +10352,7 @@ int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt)
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* This check would not have been enabled for A0 h/w, see
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* set_ctxt_jkey().
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*/
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- if (!is_a0(dd)) {
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+ if (!is_ax(dd)) {
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reg = read_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE);
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reg &= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
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write_kctxt_csr(dd, sctxt, SEND_CTXT_CHECK_ENABLE, reg);
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