|
@@ -76,6 +76,7 @@
|
|
#include "amdgpu_acp.h"
|
|
#include "amdgpu_acp.h"
|
|
#endif
|
|
#endif
|
|
#include "dce_virtual.h"
|
|
#include "dce_virtual.h"
|
|
|
|
+#include "mxgpu_vi.h"
|
|
|
|
|
|
/*
|
|
/*
|
|
* Indirect registers accessor
|
|
* Indirect registers accessor
|
|
@@ -272,6 +273,12 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
|
|
/* Some of the registers might be dependent on GRBM_GFX_INDEX */
|
|
/* Some of the registers might be dependent on GRBM_GFX_INDEX */
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
|
|
|
|
|
|
+ if (amdgpu_sriov_vf(adev)) {
|
|
|
|
+ xgpu_vi_init_golden_registers(adev);
|
|
|
|
+ mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
+ return;
|
|
|
|
+ }
|
|
|
|
+
|
|
switch (adev->asic_type) {
|
|
switch (adev->asic_type) {
|
|
case CHIP_TOPAZ:
|
|
case CHIP_TOPAZ:
|
|
amdgpu_program_register_sequence(adev,
|
|
amdgpu_program_register_sequence(adev,
|
|
@@ -921,8 +928,10 @@ static int vi_common_early_init(void *handle)
|
|
(amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
|
|
(amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
|
|
smc_enabled = true;
|
|
smc_enabled = true;
|
|
|
|
|
|
- if (amdgpu_sriov_vf(adev))
|
|
|
|
|
|
+ if (amdgpu_sriov_vf(adev)) {
|
|
amdgpu_virt_init_setting(adev);
|
|
amdgpu_virt_init_setting(adev);
|
|
|
|
+ xgpu_vi_mailbox_set_irq_funcs(adev);
|
|
|
|
+ }
|
|
|
|
|
|
adev->rev_id = vi_get_rev_id(adev);
|
|
adev->rev_id = vi_get_rev_id(adev);
|
|
adev->external_rev_id = 0xFF;
|
|
adev->external_rev_id = 0xFF;
|
|
@@ -1088,8 +1097,23 @@ static int vi_common_early_init(void *handle)
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+static int vi_common_late_init(void *handle)
|
|
|
|
+{
|
|
|
|
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
+
|
|
|
|
+ if (amdgpu_sriov_vf(adev))
|
|
|
|
+ xgpu_vi_mailbox_get_irq(adev);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
static int vi_common_sw_init(void *handle)
|
|
static int vi_common_sw_init(void *handle)
|
|
{
|
|
{
|
|
|
|
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
+
|
|
|
|
+ if (amdgpu_sriov_vf(adev))
|
|
|
|
+ xgpu_vi_mailbox_add_irq_id(adev);
|
|
|
|
+
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
@@ -1111,6 +1135,9 @@ static int vi_common_hw_init(void *handle)
|
|
/* enable the doorbell aperture */
|
|
/* enable the doorbell aperture */
|
|
vi_enable_doorbell_aperture(adev, true);
|
|
vi_enable_doorbell_aperture(adev, true);
|
|
|
|
|
|
|
|
+ if (amdgpu_sriov_vf(adev))
|
|
|
|
+ xgpu_vi_mailbox_put_irq(adev);
|
|
|
|
+
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
|
|
@@ -1431,7 +1458,7 @@ static void vi_common_get_clockgating_state(void *handle, u32 *flags)
|
|
static const struct amd_ip_funcs vi_common_ip_funcs = {
|
|
static const struct amd_ip_funcs vi_common_ip_funcs = {
|
|
.name = "vi_common",
|
|
.name = "vi_common",
|
|
.early_init = vi_common_early_init,
|
|
.early_init = vi_common_early_init,
|
|
- .late_init = NULL,
|
|
|
|
|
|
+ .late_init = vi_common_late_init,
|
|
.sw_init = vi_common_sw_init,
|
|
.sw_init = vi_common_sw_init,
|
|
.sw_fini = vi_common_sw_fini,
|
|
.sw_fini = vi_common_sw_fini,
|
|
.hw_init = vi_common_hw_init,
|
|
.hw_init = vi_common_hw_init,
|
|
@@ -1460,6 +1487,9 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
|
|
/* in early init stage, vbios code won't work */
|
|
/* in early init stage, vbios code won't work */
|
|
vi_detect_hw_virtualization(adev);
|
|
vi_detect_hw_virtualization(adev);
|
|
|
|
|
|
|
|
+ if (amdgpu_sriov_vf(adev))
|
|
|
|
+ adev->virt.ops = &xgpu_vi_virt_ops;
|
|
|
|
+
|
|
switch (adev->asic_type) {
|
|
switch (adev->asic_type) {
|
|
case CHIP_TOPAZ:
|
|
case CHIP_TOPAZ:
|
|
/* topaz has no DCE, UVD, VCE */
|
|
/* topaz has no DCE, UVD, VCE */
|