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@@ -432,7 +432,7 @@ static uint32_t iceland_smu_get_mask_for_fw_type(uint32_t fw_type)
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case AMDGPU_UCODE_ID_CP_ME:
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return UCODE_ID_CP_ME_MASK;
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case AMDGPU_UCODE_ID_CP_MEC1:
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- return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK;
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+ return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK;
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case AMDGPU_UCODE_ID_CP_MEC2:
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return UCODE_ID_CP_MEC_MASK;
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case AMDGPU_UCODE_ID_RLC_G:
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@@ -522,12 +522,6 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
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return -EINVAL;
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}
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- if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
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- &toc->entry[toc->num_entries++])) {
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- DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
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- return -EINVAL;
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- }
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-
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if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
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&toc->entry[toc->num_entries++])) {
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DRM_ERROR("Failed to get firmware entry for SDMA0\n");
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@@ -550,8 +544,8 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
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UCODE_ID_CP_ME_MASK |
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UCODE_ID_CP_PFP_MASK |
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UCODE_ID_CP_MEC_MASK |
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- UCODE_ID_CP_MEC_JT1_MASK |
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- UCODE_ID_CP_MEC_JT2_MASK;
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+ UCODE_ID_CP_MEC_JT1_MASK;
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+
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if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
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DRM_ERROR("Fail to request SMU load ucode\n");
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