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@@ -3042,6 +3042,24 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_
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DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
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}
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+static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
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+{
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+ uint8_t psr_caps = 0;
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+
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+ drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
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+ return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
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+}
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+
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+static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
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+{
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+ uint8_t dprx = 0;
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+
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+ drm_dp_dpcd_readb(&intel_dp->aux,
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+ DP_DPRX_FEATURE_ENUMERATION_LIST,
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+ &dprx);
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+ return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
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+}
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+
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/* These are source-specific values. */
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uint8_t
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intel_dp_voltage_max(struct intel_dp *intel_dp)
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@@ -3620,6 +3638,14 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
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dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
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DRM_DEBUG_KMS("PSR2 %s on sink",
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dev_priv->psr.psr2_support ? "supported" : "not supported");
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+
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+ if (dev_priv->psr.psr2_support) {
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+ dev_priv->psr.y_cord_support =
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+ intel_dp_get_y_cord_status(intel_dp);
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+ dev_priv->psr.colorimetry_support =
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+ intel_dp_get_colorimetry_status(intel_dp);
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+ }
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+
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}
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/* Read the eDP Display control capabilities registers */
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