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@@ -191,6 +191,8 @@ static struct clk_div_table axi_div_table[] = {
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static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
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0x050, 0, 3, axi_div_table, 0);
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+#define SUN6I_A31_AHB1_REG 0x054
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+
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static const char * const ahb1_parents[] = { "osc32k", "osc24M",
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"axi", "pll-periph" };
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@@ -1230,6 +1232,16 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node)
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val &= BIT(16);
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writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
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+ /* Force AHB1 to PLL6 / 3 */
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+ val = readl(reg + SUN6I_A31_AHB1_REG);
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+ /* set PLL6 pre-div = 3 */
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+ val &= ~GENMASK(7, 6);
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+ val |= 0x2 << 6;
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+ /* select PLL6 / pre-div */
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+ val &= ~GENMASK(13, 12);
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+ val |= 0x3 << 12;
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+ writel(val, reg + SUN6I_A31_AHB1_REG);
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+
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sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
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ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
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