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+/dts-v1/;
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+
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+#include "skeleton.dtsi"
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+
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+/ {
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+ model = "Qualcomm APQ 8084";
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+ compatible = "qcom,apq8084";
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+ interrupt-parent = <&intc>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ compatible = "qcom,krait";
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+ reg = <0>;
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc0>;
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+ };
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+
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+ cpu@1 {
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+ device_type = "cpu";
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+ compatible = "qcom,krait";
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+ reg = <1>;
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc1>;
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+ };
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+
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+ cpu@2 {
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+ device_type = "cpu";
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+ compatible = "qcom,krait";
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+ reg = <2>;
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc2>;
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+ };
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+
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+ cpu@3 {
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+ device_type = "cpu";
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+ compatible = "qcom,krait";
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+ reg = <3>;
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+ enable-method = "qcom,kpss-acc-v2";
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc3>;
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+ };
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+
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+ L2: l2-cache {
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+ compatible = "qcom,arch-cache";
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+ cache-level = <2>;
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+ qcom,saw = <&saw_l2>;
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+ };
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+ };
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+
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+ cpu-pmu {
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+ compatible = "qcom,krait-pmu";
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+ interrupts = <1 7 0xf04>;
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+ };
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+
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+ timer {
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+ compatible = "arm,armv7-timer";
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+ interrupts = <1 2 0xf08>,
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+ <1 3 0xf08>,
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+ <1 4 0xf08>,
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+ <1 1 0xf08>;
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+ clock-frequency = <19200000>;
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+ };
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+
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+ soc: soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "simple-bus";
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+
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+ intc: interrupt-controller@f9000000 {
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+ compatible = "qcom,msm-qgic2";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = <0xf9000000 0x1000>,
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+ <0xf9002000 0x1000>;
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+ };
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+
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+ timer@f9020000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "arm,armv7-timer-mem";
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+ reg = <0xf9020000 0x1000>;
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+ clock-frequency = <19200000>;
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+
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+ frame@f9021000 {
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+ frame-number = <0>;
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+ interrupts = <0 8 0x4>,
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+ <0 7 0x4>;
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+ reg = <0xf9021000 0x1000>,
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+ <0xf9022000 0x1000>;
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+ };
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+
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+ frame@f9023000 {
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+ frame-number = <1>;
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+ interrupts = <0 9 0x4>;
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+ reg = <0xf9023000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9024000 {
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+ frame-number = <2>;
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+ interrupts = <0 10 0x4>;
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+ reg = <0xf9024000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9025000 {
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+ frame-number = <3>;
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+ interrupts = <0 11 0x4>;
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+ reg = <0xf9025000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9026000 {
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+ frame-number = <4>;
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+ interrupts = <0 12 0x4>;
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+ reg = <0xf9026000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9027000 {
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+ frame-number = <5>;
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+ interrupts = <0 13 0x4>;
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+ reg = <0xf9027000 0x1000>;
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+ status = "disabled";
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+ };
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+
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+ frame@f9028000 {
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+ frame-number = <6>;
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+ interrupts = <0 14 0x4>;
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+ reg = <0xf9028000 0x1000>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ saw_l2: regulator@f9012000 {
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+ compatible = "qcom,saw2";
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+ reg = <0xf9012000 0x1000>;
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+ regulator;
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+ };
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+
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+ acc0: clock-controller@f9088000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf9088000 0x1000>,
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+ <0xf9008000 0x1000>;
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+ };
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+
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+ acc1: clock-controller@f9098000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf9098000 0x1000>,
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+ <0xf9008000 0x1000>;
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+ };
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+
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+ acc2: clock-controller@f90a8000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf90a8000 0x1000>,
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+ <0xf9008000 0x1000>;
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+ };
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+
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+ acc3: clock-controller@f90b8000 {
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+ compatible = "qcom,kpss-acc-v2";
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+ reg = <0xf90b8000 0x1000>,
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+ <0xf9008000 0x1000>;
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+ };
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+
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+ restart@fc4ab000 {
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+ compatible = "qcom,pshold";
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+ reg = <0xfc4ab000 0x4>;
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+ };
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+ };
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+};
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