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@@ -17,7 +17,7 @@ logical_chip_type_t getChipType(void)
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char physicalRev;
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char physicalRev;
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logical_chip_type_t chip;
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logical_chip_type_t chip;
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- physicalID = devId750; /* either 0x718 or 0x750 */
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+ physicalID = devId750;//either 0x718 or 0x750
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physicalRev = revId750;
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physicalRev = revId750;
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if (physicalID == 0x718)
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if (physicalID == 0x718)
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@@ -257,7 +257,7 @@ int ddk750_initHw(initchip_param_t *pInitParam)
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unsigned int ulReg;
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unsigned int ulReg;
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#if 0
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#if 0
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- /* move the code to map regiter function. */
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+ //move the code to map regiter function.
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if (getChipType() == SM718) {
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if (getChipType() == SM718) {
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/* turn on big endian bit*/
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/* turn on big endian bit*/
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ulReg = PEEK32(0x74);
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ulReg = PEEK32(0x74);
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@@ -488,6 +488,7 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll)
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}
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}
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}
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}
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+ //printk("Finally: pll->n[%lu],m[%lu],od[%lu],pod[%lu]\n",pll->N,pll->M,pll->OD,pll->POD);
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return ret;
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return ret;
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}
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}
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@@ -579,9 +580,14 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
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}
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}
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/* Restore input frequency from Khz to hz unit */
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/* Restore input frequency from Khz to hz unit */
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+// pPLL->inputFreq *= 1000;
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ulRequestClk *= 1000;
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ulRequestClk *= 1000;
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pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
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pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
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+ /* Output debug information */
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+ //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency = %d\n", ulRequestClk));
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+ //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD));
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+
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/* Return actual frequency that the PLL can set */
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/* Return actual frequency that the PLL can set */
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ret = calcPLL(pPLL);
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ret = calcPLL(pPLL);
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return ret;
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return ret;
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