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@@ -721,13 +721,10 @@ static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
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return ret;
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}
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-static __init int perf_event_ibs_init(void)
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+static __init void perf_event_ibs_init(void)
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{
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struct attribute **attr = ibs_op_format_attrs;
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- if (!ibs_caps)
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- return -ENODEV; /* ibs not supported by the cpu */
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-
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perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
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if (ibs_caps & IBS_CAPS_OPCNT) {
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@@ -738,13 +735,11 @@ static __init int perf_event_ibs_init(void)
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register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
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pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
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-
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- return 0;
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}
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#else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
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-static __init int perf_event_ibs_init(void) { return 0; }
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+static __init void perf_event_ibs_init(void) { }
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#endif
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@@ -921,7 +916,7 @@ static inline int get_ibs_lvt_offset(void)
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return val & IBSCTL_LVT_OFFSET_MASK;
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}
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-static void setup_APIC_ibs(void *dummy)
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+static void setup_APIC_ibs(void)
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{
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int offset;
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@@ -936,7 +931,7 @@ failed:
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smp_processor_id());
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}
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-static void clear_APIC_ibs(void *dummy)
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+static void clear_APIC_ibs(void)
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{
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int offset;
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@@ -945,18 +940,24 @@ static void clear_APIC_ibs(void *dummy)
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setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
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}
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+static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
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+{
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+ setup_APIC_ibs();
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+ return 0;
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+}
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+
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#ifdef CONFIG_PM
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static int perf_ibs_suspend(void)
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{
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- clear_APIC_ibs(NULL);
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+ clear_APIC_ibs();
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return 0;
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}
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static void perf_ibs_resume(void)
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{
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ibs_eilvt_setup();
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- setup_APIC_ibs(NULL);
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+ setup_APIC_ibs();
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}
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static struct syscore_ops perf_ibs_syscore_ops = {
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@@ -975,27 +976,15 @@ static inline void perf_ibs_pm_init(void) { }
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#endif
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-static int
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-perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
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+static int x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)
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{
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- switch (action & ~CPU_TASKS_FROZEN) {
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- case CPU_STARTING:
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- setup_APIC_ibs(NULL);
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- break;
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- case CPU_DYING:
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- clear_APIC_ibs(NULL);
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- break;
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- default:
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- break;
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- }
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-
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- return NOTIFY_OK;
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+ clear_APIC_ibs();
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+ return 0;
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}
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static __init int amd_ibs_init(void)
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{
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u32 caps;
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- int ret = -EINVAL;
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caps = __get_ibs_caps();
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if (!caps)
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@@ -1004,22 +993,25 @@ static __init int amd_ibs_init(void)
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ibs_eilvt_setup();
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if (!ibs_eilvt_valid())
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- goto out;
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+ return -EINVAL;
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perf_ibs_pm_init();
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- cpu_notifier_register_begin();
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+
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ibs_caps = caps;
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/* make ibs_caps visible to other cpus: */
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smp_mb();
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- smp_call_function(setup_APIC_ibs, NULL, 1);
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- __perf_cpu_notifier(perf_ibs_cpu_notifier);
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- cpu_notifier_register_done();
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+ /*
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+ * x86_pmu_amd_ibs_starting_cpu will be called from core on
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+ * all online cpus.
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+ */
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+ cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
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+ "AP_PERF_X86_AMD_IBS_STARTING",
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+ x86_pmu_amd_ibs_starting_cpu,
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+ x86_pmu_amd_ibs_dying_cpu);
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- ret = perf_event_ibs_init();
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-out:
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- if (ret)
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- pr_err("Failed to setup IBS, %d\n", ret);
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- return ret;
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+ perf_event_ibs_init();
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+
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+ return 0;
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}
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/* Since we need the pci subsystem to init ibs we can't do this earlier: */
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