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@@ -1159,6 +1159,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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struct arm_smmu_domain *smmu_domain = domain->priv;
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struct arm_smmu_device *device_smmu = dev->archdata.iommu;
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struct arm_smmu_master *master;
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+ unsigned long flags;
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if (!device_smmu) {
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dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
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@@ -1169,7 +1170,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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* Sanity check the domain. We don't currently support domains
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* that cross between different SMMU chains.
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*/
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- spin_lock(&smmu_domain->lock);
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+ spin_lock_irqsave(&smmu_domain->lock, flags);
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if (!smmu_domain->leaf_smmu) {
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/* Now that we have a master, we can finalise the domain */
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ret = arm_smmu_init_domain_context(domain, dev);
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@@ -1184,7 +1185,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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dev_name(device_smmu->dev));
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goto err_unlock;
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}
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- spin_unlock(&smmu_domain->lock);
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+ spin_unlock_irqrestore(&smmu_domain->lock, flags);
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/* Looks ok, so add the device to the domain */
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master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
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@@ -1194,7 +1195,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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return arm_smmu_domain_add_master(smmu_domain, master);
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err_unlock:
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- spin_unlock(&smmu_domain->lock);
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+ spin_unlock_irqrestore(&smmu_domain->lock, flags);
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return ret;
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}
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@@ -1396,6 +1397,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
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pgd_t *pgd = root_cfg->pgd;
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struct arm_smmu_device *smmu = root_cfg->smmu;
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+ unsigned long irqflags;
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if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
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stage = 2;
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@@ -1418,7 +1420,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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if (paddr & ~output_mask)
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return -ERANGE;
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- spin_lock(&smmu_domain->lock);
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+ spin_lock_irqsave(&smmu_domain->lock, irqflags);
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pgd += pgd_index(iova);
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end = iova + size;
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do {
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@@ -1434,7 +1436,7 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
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} while (pgd++, iova != end);
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out_unlock:
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- spin_unlock(&smmu_domain->lock);
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+ spin_unlock_irqrestore(&smmu_domain->lock, irqflags);
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return ret;
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}
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