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@@ -119,6 +119,25 @@ static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
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clk_disable_unprepare(imx->clk_per);
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clk_disable_unprepare(imx->clk_per);
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}
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}
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+static void imx_pwm_sw_reset(struct pwm_chip *chip)
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+{
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+ struct imx_chip *imx = to_imx_chip(chip);
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+ struct device *dev = chip->dev;
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+ int wait_count = 0;
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+ u32 cr;
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+
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+ writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
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+ do {
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+ usleep_range(200, 1000);
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+ cr = readl(imx->mmio_base + MX3_PWMCR);
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+ } while ((cr & MX3_PWMCR_SWR) &&
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+ (wait_count++ < MX3_PWM_SWR_LOOP));
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+
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+ if (cr & MX3_PWMCR_SWR)
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+ dev_warn(dev, "software reset timeout\n");
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+}
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+
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+
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static int imx_pwm_config_v2(struct pwm_chip *chip,
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static int imx_pwm_config_v2(struct pwm_chip *chip,
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struct pwm_device *pwm, int duty_ns, int period_ns)
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struct pwm_device *pwm, int duty_ns, int period_ns)
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{
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{
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@@ -128,7 +147,7 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
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unsigned long period_cycles, duty_cycles, prescale;
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unsigned long period_cycles, duty_cycles, prescale;
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unsigned int period_ms;
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unsigned int period_ms;
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bool enable = pwm_is_enabled(pwm);
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bool enable = pwm_is_enabled(pwm);
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- int wait_count = 0, fifoav;
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+ int fifoav;
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u32 cr, sr;
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u32 cr, sr;
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/*
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/*
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@@ -151,15 +170,7 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
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dev_warn(dev, "there is no free FIFO slot\n");
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dev_warn(dev, "there is no free FIFO slot\n");
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}
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}
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} else {
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} else {
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- writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
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- do {
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- usleep_range(200, 1000);
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- cr = readl(imx->mmio_base + MX3_PWMCR);
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- } while ((cr & MX3_PWMCR_SWR) &&
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- (wait_count++ < MX3_PWM_SWR_LOOP));
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-
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- if (cr & MX3_PWMCR_SWR)
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- dev_warn(dev, "software reset timeout\n");
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+ imx_pwm_sw_reset(chip);
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}
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}
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c = clk_get_rate(imx->clk_per);
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c = clk_get_rate(imx->clk_per);
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