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@@ -552,7 +552,7 @@ void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
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schedule_work(&host->done);
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}
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-static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
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+static void tmio_mmc_data_irq(struct tmio_mmc_host *host, unsigned int stat)
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{
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struct mmc_data *data;
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spin_lock(&host->lock);
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@@ -561,6 +561,9 @@ static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
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if (!data)
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goto out;
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+ if (stat & TMIO_STAT_CRCFAIL || stat & TMIO_STAT_STOPBIT_ERR ||
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+ stat & TMIO_STAT_TXUNDERRUN)
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+ data->error = -EILSEQ;
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if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
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u32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
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bool done = false;
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@@ -609,8 +612,6 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
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goto out;
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}
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- host->cmd = NULL;
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-
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/* This controller is sicker than the PXA one. Not only do we need to
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* drop the top 8 bits of the first response word, we also need to
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* modify the order of the response for short response command types.
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@@ -630,14 +631,16 @@ static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
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if (stat & TMIO_STAT_CMDTIMEOUT)
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cmd->error = -ETIMEDOUT;
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- else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
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+ else if ((stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC) ||
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+ stat & TMIO_STAT_STOPBIT_ERR ||
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+ stat & TMIO_STAT_CMD_IDX_ERR)
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cmd->error = -EILSEQ;
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/* If there is data to handle we enable data IRQs here, and
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* we will ultimatley finish the request in the data_end handler.
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* If theres no data or we encountered an error, finish now.
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*/
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- if (host->data && !cmd->error) {
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+ if (host->data && (!cmd->error || cmd->error == -EILSEQ)) {
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if (host->data->flags & MMC_DATA_READ) {
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if (host->force_pio || !host->chan_rx)
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tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
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@@ -698,7 +701,7 @@ static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
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/* Data transfer completion */
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if (ireg & TMIO_STAT_DATAEND) {
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tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
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- tmio_mmc_data_irq(host);
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+ tmio_mmc_data_irq(host, status);
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return true;
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}
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