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@@ -747,6 +747,69 @@ static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
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}
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}
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+static int vf610_nfc_attach_chip(struct nand_chip *chip)
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+{
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+ struct mtd_info *mtd = nand_to_mtd(chip);
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+ struct vf610_nfc *nfc = mtd_to_nfc(mtd);
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+
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+ vf610_nfc_init_controller(nfc);
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+
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+ /* Bad block options. */
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+ if (chip->bbt_options & NAND_BBT_USE_FLASH)
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+ chip->bbt_options |= NAND_BBT_NO_OOB;
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+
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+ /* Single buffer only, max 256 OOB minus ECC status */
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+ if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
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+ dev_err(nfc->dev, "Unsupported flash page size\n");
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+ return -ENXIO;
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+ }
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+
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+ if (chip->ecc.mode != NAND_ECC_HW)
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+ return 0;
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+
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+ if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
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+ dev_err(nfc->dev, "Unsupported flash with hwecc\n");
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+ return -ENXIO;
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+ }
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+
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+ if (chip->ecc.size != mtd->writesize) {
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+ dev_err(nfc->dev, "Step size needs to be page size\n");
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+ return -ENXIO;
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+ }
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+
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+ /* Only 64 byte ECC layouts known */
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+ if (mtd->oobsize > 64)
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+ mtd->oobsize = 64;
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+
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+ /* Use default large page ECC layout defined in NAND core */
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+ mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
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+ if (chip->ecc.strength == 32) {
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+ nfc->ecc_mode = ECC_60_BYTE;
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+ chip->ecc.bytes = 60;
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+ } else if (chip->ecc.strength == 24) {
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+ nfc->ecc_mode = ECC_45_BYTE;
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+ chip->ecc.bytes = 45;
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+ } else {
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+ dev_err(nfc->dev, "Unsupported ECC strength\n");
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+ return -ENXIO;
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+ }
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+
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+ chip->ecc.read_page = vf610_nfc_read_page;
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+ chip->ecc.write_page = vf610_nfc_write_page;
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+ chip->ecc.read_page_raw = vf610_nfc_read_page_raw;
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+ chip->ecc.write_page_raw = vf610_nfc_write_page_raw;
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+ chip->ecc.read_oob = vf610_nfc_read_oob;
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+ chip->ecc.write_oob = vf610_nfc_write_oob;
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+
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+ chip->ecc.size = PAGE_2K;
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+
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+ return 0;
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+}
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+
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+static const struct nand_controller_ops vf610_nfc_controller_ops = {
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+ .attach_chip = vf610_nfc_attach_chip,
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+};
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+
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static int vf610_nfc_probe(struct platform_device *pdev)
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{
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struct vf610_nfc *nfc;
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@@ -827,67 +890,9 @@ static int vf610_nfc_probe(struct platform_device *pdev)
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vf610_nfc_preinit_controller(nfc);
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- /* first scan to find the device and get the page size */
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- err = nand_scan_ident(mtd, 1, NULL);
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- if (err)
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- goto err_disable_clk;
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-
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- vf610_nfc_init_controller(nfc);
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-
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- /* Bad block options. */
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- if (chip->bbt_options & NAND_BBT_USE_FLASH)
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- chip->bbt_options |= NAND_BBT_NO_OOB;
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-
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- /* Single buffer only, max 256 OOB minus ECC status */
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- if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
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- dev_err(nfc->dev, "Unsupported flash page size\n");
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- err = -ENXIO;
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- goto err_disable_clk;
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- }
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-
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- if (chip->ecc.mode == NAND_ECC_HW) {
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- if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
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- dev_err(nfc->dev, "Unsupported flash with hwecc\n");
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- err = -ENXIO;
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- goto err_disable_clk;
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- }
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-
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- if (chip->ecc.size != mtd->writesize) {
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- dev_err(nfc->dev, "Step size needs to be page size\n");
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- err = -ENXIO;
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- goto err_disable_clk;
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- }
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-
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- /* Only 64 byte ECC layouts known */
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- if (mtd->oobsize > 64)
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- mtd->oobsize = 64;
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-
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- /* Use default large page ECC layout defined in NAND core */
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- mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
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- if (chip->ecc.strength == 32) {
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- nfc->ecc_mode = ECC_60_BYTE;
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- chip->ecc.bytes = 60;
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- } else if (chip->ecc.strength == 24) {
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- nfc->ecc_mode = ECC_45_BYTE;
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- chip->ecc.bytes = 45;
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- } else {
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- dev_err(nfc->dev, "Unsupported ECC strength\n");
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- err = -ENXIO;
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- goto err_disable_clk;
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- }
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-
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- chip->ecc.read_page = vf610_nfc_read_page;
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- chip->ecc.write_page = vf610_nfc_write_page;
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- chip->ecc.read_page_raw = vf610_nfc_read_page_raw;
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- chip->ecc.write_page_raw = vf610_nfc_write_page_raw;
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- chip->ecc.read_oob = vf610_nfc_read_oob;
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- chip->ecc.write_oob = vf610_nfc_write_oob;
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-
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- chip->ecc.size = PAGE_2K;
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- }
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-
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- /* second phase scan */
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- err = nand_scan_tail(mtd);
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+ /* Scan the NAND chip */
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+ chip->dummy_controller.ops = &vf610_nfc_controller_ops;
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+ err = nand_scan(mtd, 1);
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if (err)
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goto err_disable_clk;
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