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@@ -35,12 +35,27 @@ enum {
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/* SCSMR (Serial Mode Register) */
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+#define SCSMR_C_A BIT(7) /* Communication Mode */
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+#define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
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+#define SCSMR_ASYNC 0 /* - Asynchronous mode */
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#define SCSMR_CHR BIT(6) /* 7-bit Character Length */
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#define SCSMR_PE BIT(5) /* Parity Enable */
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#define SCSMR_ODD BIT(4) /* Odd Parity */
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#define SCSMR_STOP BIT(3) /* Stop Bit Length */
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#define SCSMR_CKS 0x0003 /* Clock Select */
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+/* Serial Mode Register, SCIFA/SCIFB only bits */
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+#define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */
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+#define SCSMR_SRC_MASK 0x0700 /* Sampling Control */
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+#define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */
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+#define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */
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+#define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */
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+#define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */
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+#define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */
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+#define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */
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+#define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */
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+#define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */
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+
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/* Serial Control Register, SCIFA/SCIFB only bits */
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#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
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#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
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