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@@ -62,15 +62,15 @@
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#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
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#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
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#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
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-#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
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-#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
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-#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
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+#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
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+#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
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+#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
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/* Interrupt Enable */
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-#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
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-#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
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-#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
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-#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
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+#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
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+#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
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+#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
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+#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
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#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
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#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
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#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
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@@ -79,7 +79,7 @@
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#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
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#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
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-#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
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+#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
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/* Interrupt status */
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#define SIRFSOC_SPI_RX_DONE BIT(0)
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