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@@ -119,6 +119,10 @@
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#define RL5C4XX_MISC_CONTROL 0x2F /* 8 bit */
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#define RL5C4XX_ZV_ENABLE 0x08
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+/* Misc Control 3 Register */
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+#define RL5C4XX_MISC3 0x00A2 /* 16 bit */
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+#define RL5C47X_MISC3_CB_CLKRUN_DIS BIT(1)
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+
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#ifdef __YENTA_H
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#define rl_misc(socket) ((socket)->private[0])
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@@ -156,6 +160,35 @@ static void ricoh_set_zv(struct yenta_socket *socket)
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}
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}
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+static void ricoh_set_clkrun(struct yenta_socket *socket, bool quiet)
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+{
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+ u16 misc3;
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+
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+ /*
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+ * RL5C475II likely has this setting, too, however no datasheet
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+ * is publicly available for this chip
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+ */
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+ if (socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C476 &&
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+ socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C478)
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+ return;
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+
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+ if (socket->dev->revision < 0x80)
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+ return;
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+
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+ misc3 = config_readw(socket, RL5C4XX_MISC3);
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+ if (misc3 & RL5C47X_MISC3_CB_CLKRUN_DIS) {
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+ if (!quiet)
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+ dev_dbg(&socket->dev->dev,
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+ "CLKRUN feature already disabled\n");
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+ } else if (disable_clkrun) {
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+ if (!quiet)
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+ dev_info(&socket->dev->dev,
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+ "Disabling CLKRUN feature\n");
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+ misc3 |= RL5C47X_MISC3_CB_CLKRUN_DIS;
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+ config_writew(socket, RL5C4XX_MISC3, misc3);
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+ }
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+}
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+
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static void ricoh_save_state(struct yenta_socket *socket)
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{
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rl_misc(socket) = config_readw(socket, RL5C4XX_MISC);
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@@ -172,6 +205,7 @@ static void ricoh_restore_state(struct yenta_socket *socket)
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config_writew(socket, RL5C4XX_16BIT_IO_0, rl_io(socket));
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config_writew(socket, RL5C4XX_16BIT_MEM_0, rl_mem(socket));
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config_writew(socket, RL5C4XX_CONFIG, rl_config(socket));
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+ ricoh_set_clkrun(socket, true);
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}
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@@ -197,6 +231,7 @@ static int ricoh_override(struct yenta_socket *socket)
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config_writew(socket, RL5C4XX_CONFIG, config);
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ricoh_set_zv(socket);
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+ ricoh_set_clkrun(socket, false);
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return 0;
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}
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